AMD Smart MP Technology

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Smart MP Technology is the AMD PR term for their multiprocessor platform. A combination of the Athlon MP processor and the AMD-760 MP chipset delivers a ‘smarter’ implementation for multiprocessing.

The main drawing power of the Smart MP technology is the dual point-to-point, high-speed 266 MHz Athlon system busses. Having a dedicated bus per processor allows the system to perform better, simply because it is designed to provide up to 4.2 GB/s of bus bandwidth in a dual-processor system. Also included on the bus architecture is a newer transaction-based protocol that allows each processor to continue working independently while outstanding data requests are being filled by the chipset and memory.

An optimized MOESI (Modified Owner Exclusive Shared Invalid) is included with the AMD-760 MP chipset as well. This complex set of protocols and instructions is responsible for the processor cache coherency. Basically, it keeps track of the data that is stored in each CPUs cache. The MOESI identifies when data from one processor is needed by another and when the data is shared between them. It then can transfer and/or remove the data from cache to cache without having to bog down the memory traffic. In effect, it is nearly doubling the size of the L1 and L2 caches, since each processor can share the other’s data on a much faster scale than the rest of the system bus. This then frees up the memory traffic that WOULD have been used to access data the processors need, increasing available bandwidth of the FSB as a whole. These busses between the two processors are called ‘Snoop Busses’.

AMD Athlon MP and AMD-760MP Chipset Technology - Chipsets 16

From this diagram, you can see illustrated how the point-to-point bus differs from the shared bus system.

AMD Athlon MP and AMD-760MP Chipset Technology - Chipsets 17

And here, you can see how the “Snoop” bus works to reduce memory bandwidth, freeing it up for use elsewhere.

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