Architecture Overview

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The core logic, what we have commonly called the chipset, for the AMD Opteron processor is going to be jump started (as always) by AMD’s own AMD-8000 series. This core logic set comes in three different parts, though it will not be necessary for motherboard developers to use them all.

The AMD-8151 AGP3.0 Graphics Tunnel is what we might have previously called the “north bridge.” However, because the memory controller has been moved on to the processor, the main job of this piece of the core logic is handling the graphics implementation. This piece offers a 16-bit HyperTransport (will be abbreviated HT) interface to the processors offering a 6.4 GB/s bandwidth rate. It also has an 8-bit HT interface to the rest of the system, allowing 1.6 GB/s worth of components to be daisy-chained off of it. It is compliant with the AGP 3.0 specifications and supports transfer rates up to 8x. Also, it will be backwards compatible with current AGP 2.0 standard and 1x, 2x and 4x speeds.

The AMD-8131 PCI-X Tunnel is a high-speed device that provides two independent PCI-X bus bridges. This is a feature that will become very important as the Opteron enters the enterprise server market. The 8131 also offer a 16-bit HT interface back to the CPU for 6.4 GB/s of bandwidth as well as an 8-bit HT interface offering 3.2 GB/s of bandwidth to the rest of the system that is attached to it. Both the PCI-X bridges on each 8131 will support both the PCI-X and the PCI 2.2 modes. In PCI-X mode, it offers 133 MHz, 100 MHz, 66 MHz and 33 MHz transfer rates and for PCI 2.2 it will offer 66 MHz and 33 MHz modes. The transfer rates and modes of each bridge are completely independent meaning the AMD-8131 can support a PCI 2.2 bridge running at 33 MHz and a PCI-X bridge at 133 MHz or any other combination with up to 5 PCI slots on each bridge.

Finally, the AMD-8111 I/O Hub will be replacing what we know of as the “south bridge” and will integrate the storage, connectivity, audio, I/O expansion, security and system management into a single chip. The 8111 will have an 8-bit HT interface with its master device offering 800 MB/s of bandwidth. Though that is less than what we have seen on the other tunnels, it is more than adequate for the devices that are integrated to it. Some of the features of this chip will include the PCI 2.2 standards, AC-97 audio, 10/100 Ethernet, USB controllers, ATA133, LPC bus, timers and the IOAPIC controller.

A diagram of the Opteron processor is pictured below.

AMD Opteron Processor Overview - Processors 10

The DDR memory controller that is integrated into the processor itself is a unique feature to processors, as we know them now. AMD designed the controller to remove the memory bottlenecks in current systems by scaling the memory bandwidth as more processors are added and as CPU frequency increases. The memory controller operates at the processors frequency (1:1 scaling). The dual channel DDR memory interface with a 128-bit bus gives the system up to 8.4 GB/s (PC2100) or 10.8 GB/s (PC2700) memory bandwidth on dual processing with the AMD Opteron processors.

The Opteron processor core (the architecture of which no name has yet been announced) is the 8th generation processor core from AMD. It is designed with the balance of operating frequency and IPC in mind, making it able to deliver the performance for current and future applications. In it, we are also getting the x86-64 technology that is designed to bring AMD’s customers a gradual 64-bit migration option, rather than a 64-bit only option. This gives the user a platform to which they can be satisfied with their 32-bit performance as well as a needed basis for 64-bit processing. With 64-bit options, the market can use the Opteron for large memory addressing applications such as databases, ERP and scientific research and modeling.

AMD is estimating that the Opteron processor will be 20-25% faster than the Athlon processor. 20% of this difference will come on-chip low latency memory controller and the remaining 5% will come from core changes.

The Opteron processor will be able to have up to 1 MB of on chip L2 cache and thus will improve the throughput on such apps as web servers and other large datasets.

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