“In my previous work, I’ve looked in some detail at the x86-64 instruction set, but I’ve never talked about the microarchitecture of processors that implement it. The present series of articles fills that gap by taking a close look at the architecture that underlies AMD’s Hammer-based Opteron and Athlon 64 lines. In Part I of this series, we’ll take a look at Hammer’s overall design approach. We’ll also discuss some of the problems with the x86 instruction set that Hammer’s front end is designed to solve, before examining in detail how the processor handles instruction fetching and decoding. “
Source: Ars Technica
A good technical article posted at Ars Technica, on the inner workings of AMD’s 64bit architecture, and how it works. It describes the differences between x86’s 64 bit Hammer and it’s K-7 predecessors as well as the PowerPC 601.