A New Micro-Architecture
Even though PCPer isn’t in San Francisco for this fall’s IDF, that doesn’t mean we are going to let the information pass us by. We grabbed some slides from Intel’s presentation of their new architecture to share with you all.
Missing in Action
Yes, it is true, I couldn’t make it to this fall’s Intel Developer Forum in San Francisco to cover all the information and news coming out of the Moscone Center, but that doesn’t mean PC Perspective is going to let it fall through the cracks. I was able to get a hold of the slides from yesterday’s presentation on Intel’s new micro-architecture that is set to debut late in 2006.
The slides below will guide our quick discussion and we’ll insert some more information that we have that isn’t on the slides where pertinent.
This slide is a quick view of the updated Intel roadmap through 2007 and beyond. These are color coded as well to indicate the number of cores the processors are going to support. You can see that through the end of 2005, we are still only seeing products that we are already aware of and learned about at this past spring’s IDF. The Presler and Cedar Mill cores are 65nm die shrinks of current NetBurst-based Pentium processors and the Yonah is the next coming of the Pentium M in multi-core.
What is new here are the terms Conroe, Merom, Woodcrest, Tulsa, Montvale and beyond. These are the codenames for the new processors based on a new architecture Intel is discussing at IDF right now.
The second slide here translates what the color coding on the first slide tried to indicate: Intel’s processor line up is going to be nearly all multi-core by 2006, with expectation of over 70% in mobile and desktop markets and over 85% in the server market (white/black bar).
A “re-live the past” slide, Intel summaries the past cores and the processors that bore their design. The most recent ones enthusiasts are aware of are the NetBurst technology in every Pentium 4 processor and all current Pentium D and XEs, as well as the Banias core that led to the Pentium M mobile processor.
Intel’s next architecture is still going to be based on the IA-32 instruction set, of course, but the interesting aspect here is that all three markets (server/desktop/mobile) are going to share the same common micro-architecture between them. They give the term “productized implementations” to the individual processors which basically translates into modify the cores to fit each market accordingly. Mobile CPUs will have more power management, for example.
You can see that even in the common architecture Intel has focused on lower power and scalability, a big problem with their current line up.
The new architecture has not yet been named, so this might get a little confusing at times. This slide shows that the new micro-architecture was in-fact derived from taking features from the Banias and NetBurst cores, adding in some “new innovations”, mixing and: presto! In all likeliness Intel will be taking the best features from each previous architecture and making sure they are around for the new one. Power optimization from Banias is listed as is 64-bit support from the NetBurst cores.
Some more details on the architecture are seen on this slide. It will still be an out-of-order engine despite some information floating around otherwise recently. It has a wider design that will allow up to four actions at once. The main pipeline will be 14-stages long, which is significantly less than the 31 stages found in current Prescott core CPUs. All of these features coupled with a deeper buffer mean a much higher performance per clock for Intel’s new micro-architecture over NetBurst, and presumably Banias.
The new power capabilities of the architecture are going to allow for a much broader range of efficiency, especially those targeted at the mobile market. You can expect to see variable voltages running to each core. In this same fashion, the L2 cache system has been much improved to allow for scalability as well; portions of the L2 cache will be able to virtually and physically turn off when not in use to save power. The L2 cache will be shared between the two cores to reduce any latency of bus between them and the direct L1 cache transfers between cores should improve performance dramatically as well.
The new memory access functionality is not an on-die memory controller but rather an improved pre-fetch.
Using their server platforms as an example, Intel is demonstrating here that their new architecture will allow for much better performance, but more importantly, a dramatic shift and benefit to the performance per watt metric.
The scalability of the architecture itself is seen by the different configurations that Intel is created here. The same architecture is found in the dual core mobile platform on the left as in the quad core server processor on the right. The small modifications to the core on the left including a smaller L2 cache make for a more power friendly CPU while the large L2 cache eat more power but benefit the desktop and server markets.
Here are Intel’s plans for platforms for these new processors. There was very little information given out about the chipsets involved but at least we have codenames to use from now on.
Finally, Intel’s move into the 65nm production is going well; at least they tell us that. They have three new (or additions) 300mm wafer factories online by 2007 and that should keep Intel well ahead of AMD in terms of production ability.
That pretty much sums up the information that is currently available on the new micro-architecture that Intel is planning on rolling out sometime in the second half of 2006. No doubt a lot more interesting news will be leaking out of IDF this week and we’ll be sure to post it when we get it.
Feel free to discuss this new architecture in our processor forum!
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