Core Architecture Details
Here we will go step by step through some of the important sections of the Core Architecture as it was presented to us by Intel. The block diagrams will highlight the specific feature and we’ll discuss its benefits in the hardware.
The first section of the architecture is the instruction fetching, decoding and dealing with micro-operations. All of these features are ‘in-order’ meaning the instructions must be processed and passed through in a FIFO manner, meaning first in, first out. Think of this as sequential instruction access.
Towards the bottom of our diagram we have highlighted three of the pipelines that are responsible for micro-op scheduling and execution that are out-of-order components. These are essentially the ALUs and math units that perform all the math necessary for computation to occur.
The memory pipeline consists of a 2MB or 4MB cache as well as the load and store pipelines of the execution unit and is also out-of-order. They have the ability to reorder memory commands for improved performance while maintaining the required specifications of the x86 architecture.
The retirement buffer is used for handling of all the micro-op faults that occur when either memory commands can not be reordered. It keeps the illusion of a simple in-order architecture up for the software so applications have no need to recompile or tool their designs. This is an important aspect as it keeps compatibility with all previous x86 code.
