The Core 2 Duo Architecture
Intel’s next generation mobile CPU is finally here and we run it through its paces to see if the wait was worth it. Can we expect a massive performance jump as we saw on the desktop part? Read on!
Intel has been keeping us very busy here on PC Perspective these days and for good reason – the company is producing some of the most anticipated CPUs in recent memory. Finally, after all the buzz and coverage that started at IDF this past Spring we have actual Core 2 Duo CPUs to test. Last week Ryan showed (and even before that) the world that the latest desktop Core 2 Duo CPUs (aka. Conroe) from Intel can take anything AMD can muster and firmly grinds them into a fine powder in performance, power consumption, and price.
Not to be forgotten are the mobile counterparts to these new CPUs — known to the world as Merom. This new mobile CPU is the successor to the wildly successful Yonah Core Duo CPUs and comes with many new improvements including EM64T (Intel x86-64 extensions) for 64-bit processing.
Let’s first take a quick walk through the technology and history of the Conroe and Intel’s new Core Architecture again for those of you unfamiliar with the technology.
Core 2 Duo – Intel’s Core Architecture (reprinted from our Conroe article)
At this past spring IDF in San Francisco, Intel shared with the world much of the details behind the new Intel Core 2 Duo processors powered by Intel’s Core Architecture. The name of the technology behind Conroe, Merom and Woodcrest, which are all codenames for processor cores, was officially named “Core Architecture” and is the basis for all the hype that has been building at Intel for months.
Let’s see what makes the Core 2 Duo processors tick by glancing at the architecture below the hood.
Quickly stepping through these features, we first hit on the wide dynamic execution. While past AMD and Intel architectures ran on a three instructions per clock design, Intel’s Core 2 Duo can act on four instructions simultaneously. If the improved Intel macro-fusion does its job properly, the Core 2 Duo can actually perform up to five instructions per cycle. This macro-fusing technology allows the processor to take two seperate instructions, combine them into one single instruction that the CPU can handle, and perform them both at the same time, effectively increasing the amount of work that can be done.
Intel’s advanced digital media boost describes an increase in the amount of SSE calculations done per cycle in the core. With support for 128-bit multiply, add, store and load operations, the Core 2 Duo CPUs can then combine instructions to possible do more than five calculations per cycle, though this case isn’t nearly as frequent.
The ability to reorder memory operations for better performance is called smart memory access on the new Core 2 Duo processors. Intel’s architecture has the ability to determine whether or not a memory load is going to depend on one of the preceding stores (that would essentially change the data this Data X load is going to receive). If it does not, the architecture can move the command up to improve system performance. If it does, the architecture has to leave it alone to prevent any kind of data accessing errors. When this works, it can improve the out-of-order execution speed pretty dramatically and best of all, the results are transparent to the software and don’t require any compiling or coding.
Intel ‘Conroe’ Core 2 Duo Die
Advanced smart cache is the term given to Intel’s dynamically allocated L2 cache system in place on the Core 2 Duo processor. The amount of L2 cache that is being controlled by either core can be adjusted dynamically when one core is in need of more of it than the other. If only a single thread is being executed in the operating system, the primary core can take more of the L2 cache and use it to lower the memory latency hit, thus preventing the ‘cache thrashing’ when cache is full and the CPU has to go to main system memory. This can also allow for easy data sharing between cores on the CPU.
Finally, Intel’s intelligent power capability is designed to allow the system to power down and slow down as much of the processor as possible when unneeded in order to save on power and produce less heat. First they have integrated an ultra fine grained power control system that allows them to turn off portions of either core that are not in use. Another way Intel’s engineers saved power was by allowing the internal busses between the ALUs and other units to be turned down to the data size of the information they are working on.
If you would like even more details, diagrams and information on the Core Architecture technology, you should definitely check out Ryan’s article from IDF that covered this in much greater detail than we have here.