The Tech Report features a look at the 80 core processor unveiled by Intel at the ISSC.  This chip will never hit the stores, but you can bet one of it’s descendants will.  One of the more interesting features is it’s scalability … if you feed it only 11W it will run at 310 gigaFLOPS which is still well into supercomputer territory.  However, if you give it a full meal of 98W it will hit 1.0 teraFLOP, which is definitely something to brag about.

You can also find out what Ryan has discovered right here.
“The Tera-scale processor is an array of 80 “tiles” each containing a processing engine made up of a five-port router, two independent fully-pipelined single-precision floating-point multiply-accumulator (FPMAC) units, 3KB of single-cycle instruction memory, and 2KB of data memory. The two FPMACs are based on a Very Long Instruction Word-type design, much like Intel’s Itanium. They have nine-stage pipelines and are able to provide an aggregate 16 gigaFLOPS of performance. And thanks to the five-port router, each “tile” can communicate with other tiles at up to 80GB/s.”

Here are some more Processor articles from around the web:


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