Intel Next Generation CPU Technology - Penryn and Nehalem

Intel Nehalem Architecture

Intel’s next generation architecture, dubbed Nehalem, will be built on the same 45nm technology as Penryn but will be quite a dramatic shift in technology from anything we have seen in recent years. In fact, Pat Gelsinger has dubbed this move as the most dramatic architecture shift since the introduction of the front-side bus in the Pentium Pro in 1996.

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The next two slides give out a lot of information without a lot of details; though a bit more was given during the phone call. Here we see that Intel plans on using a very similar microarchitecture technology that is 4-issues wide, just as we have now with the Intel Core technology in use on the Core 2 Duo and Core 2 Extreme processors. Making a return here is the ability for single cores to run multiple threads as Intel has added a “hyper threading” like SMT feature to Nehalem.

Nehalem will also introduce the first multi-level shared cache architecture that will allow the different cores on a processor to share data at the L1 and possibly L3 cache levels in addition to the current L2 cache sharing implemented on the Core architecture. This can allow for better data sharing between cores and increase performance for highly threaded applications.

The performance enhanced dynamic power management is going to be used to allow the processor to only use the number of processor cores necessary for optimal performance and should allow CPUs with 8 cores to power down to just 2 or 4 in situations only needing those levels of performance.

Also, this architecture will fully utilize the new High K + metal 45nm process technology and the benefits it provides in transistor speed and leakage reduction.

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Here is where even more interesting information comes to light: a new platform is going to be required for the Nehalem processor as it is a dramatic shift in technology. The Nehalem core will scale from 1 to 16+ threads using 1 to 8+ cores on a single processor thanks to the use SMT technology mentioned above.

Nehalem cores will be scalable and configurable for a wide variety of market segments and will include features such as variable size caches, differing interconnects as well as on-die memory controllers for the first time in an Intel processor. Also, Pat mentioned that optional high performance integrated graphics could be included on the same processor die as well!

I would imagine that for various segments, Intel might be able to configure a single processor for a high-performance desktop system that uses discrete graphics would include 8 cores for full CPU performance; but a processor for a budget system might include only 4 processor cores, an integrated memory controller and on-die graphics controller for a better overall value.

Intel didn’t get into details on the packaging of such chips and whether they would go the route that AMD has decided to go with multiple processor sockets allowing either CPU cores or dedicated graphics/misc cores.

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Intel’s summary for us was that Penryn would be ready for the latter half of 2007 and that we would see “production” of Nehalem in 2008 which usually indicates a late 2008 or 2009 time frame for delivery.

Below I have included the Backup from the Intel presentation that gives you more details on the updates to the Penryn core including the advanced power down technology, enhanced dynamic acceleration technology, fast Radix-16 divider and super shuffle engine. Enjoy!

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