Pat Gelsinger Talks Enterprise
Intel’s Pat Gelsinger showed off news on PCI Express 3.0 and USB 3.0 as well as news on Intel’s Skulltrail platform.
Pat Gelsinger is a very recognizable figure inside Intel and his keynote addresses are always good for a brief look into the future of the enterprise level markets and even enthusiast performance platforms. This year my main interest in his talk focused on some non-Intel developed technologies as well.
As a member of the PCI-SIG, Intel is one of the main contributors to the PCI Express development of the past several years and Gelsinger showed some of the specs behind the future PCIe 3.0 design; even though PCIe 2.0 is barely on the tip of the horizon already. Where PCIe 2.0 will double the bandwidth of the current PCIe 1.0 specifications, 3.0 will double it yet again while maintaining backward compatibility with PCIe 2.0 and even PCIe 1.0.
What’s that hiding behind Pat on stage…it looks like a skull with an Intel logo in it…and quite few cores seem to be running in that Task Manager window back there too….
Another interesting bit of news that was revealed in Gelsinger’s talk was the move to USB 3.0 and the features it will offer. How does a 10x performance increase sound over current USB 2.0 speeds? It is made possible by a cable that combines optical data as well as standard copper wire data transmission and will still be backwards compatible with USB 2.0 as well; presumably with a simple connection adaptor.
Staying with the high-level material, Gelsinger showed off this slide with the first bit of AMD comparison information for performance metrics. The main point here is that Intel is showing how their move to 45nm Penryn-based parts is going to improve their performance over current 65nm CPUs, but it is also interesting to note that even in the memory-intensive SPECfp benchmark where AMD usually excels, the 45nm Penryn passes it.
No, it’s not a great picture, but this is the Skulltrail system on display at IDF. The system features dual 3.0 GHz Yorkfield processors on the Xeon-based Stoakley motherboard platform. This of course means it is using FB-DIMMs which is a bit of a let down, but we can deal with it for the performance the system is able to get. The CPUs are liquid cooled; a setup that Intel claims will be standard for all Skulltrail systems. The motherboard does have support for up to four PCIe slots and graphics cards though this one was only running two NVIDIA cards in SLI mode.
Yeah, SLI mode. See my news post here for more on that.
This slide was shown previously at the spring IDF in China, but it’s worth looking at it again. It’s the summary of feature improvements and architecture changes that will come with the release of the Nehalem core next year. Notables include the return of SMT (two threads for every core), dynamic core power management, an integrated memory controller, optional integrated graphics and more.
Here we can see the first time Intel has shown QuickPath, their answer to AMD’s HyperTransport. I am curious though, as there was very little information on this interconnect, such as what kind of speeds and bandwidth we are talking about in this technology. But, just like HT, QuickPath will allow processors to communicate with each other without a front-side bus and increase the speed to which the CPUs communicate with the outside world of the system.
QuickPath is also apparently set up for multiple “drops” as AMD’s Athlon 64 and Opteron processors are – the system diagram on the left shows a two CPU system with two QuickPath connections each while the quad-socket system has processors with four connections.
Ending the hurrah that is Nehalem for today, Intel showed working A0 silicon running not just Windows, but a very impressive looking graphics benchmark in the fore ground with lots of other things in going on behind. Notice the 16 threads running in Task Manager…yummy.
Of course Intel isn’t going to stop after Nehalem and they already have plans for the “tick” of the Westmere core (a 32nm transition of the Nehalem architecture) and the “tock” of the Sandy Bridge core (a new 32nm architecture). Nothing was really mentioned about them of course, but you can expect details to emerge as me move down the roadmap into 2008 and 2009.
