The Itanium platform’s mission-critical support is strengthened by a new feature called Core Level Lock-Step that improves the data integrity and reliability of applications by eliminating undetected errors in the core. Core Level Lock-Step joins existing Socket Level Lock-Step technology to deliver greater reliability, availability and serviceability (RAS) by guaranteeing that calculation results are consistent among the cores and sockets.
Another new feature, Demand Based Switching (DBS), reduces server power consumption during low utilization periods, which can result in energy cost savings.
The 9100 series features clock speed of up to 1.66 GHz and 667 MHz Front Side Bus (FSB) within a 104W power envelope. A three-load bus – two processors and a chipset on the same bus – provides increased bandwidth for enterprise and high-performance computing tasks.