Peer into Intel’s Future: 2008 Roadmaps

This graph is just as interesting to see laid out as the first one was: a summary of die sizes and process technologies used by Intel since the original Pentium architecture back in 1992.  You can see the ups and down in the process development at Intel by looking at the slopes of the arrows representing each architecture.  It took about 5 years for the NetBurst architecture to shrink from the 200mm^2 sizing down to 90mm^2 or so while the Core architecture only 1 year.  Based on the estimates for the Nehalem architecture included at the end of the graph, the drop looks to be as impressive. 

The Vin-Diagram-ish desktop chipset roadmap is seen above and details the upcoming Eaglelake and Tylersburg family of chipsets.  The Eaglelake chipset isn’t anything too dramatic as it adds PCIe 2.0 support and a new ICH10 south bridge to the current lineup of Bearlake chipsets already in the market.  The G45 product does get an updated integrated graphics core though I don’t expect the shift to be dramatic enough to affect NVIDIA or AMD’s offers in the IGP market.

Looking at the high-end section we see a couple of new chipsets for Q1 of 2008 – the X48 and the Intel 5400.  The X48 chipset will officially add 1600 MHz FSB support but that’s about it.  The Intel 5400 chipset is being built for the Skulltrail platform and will include 1600 MHz FSB as well though only PCIe 1.0 and will run on FB-DIMMs at 1066 MHz.  The LGA771 socket on it, used for Xeon processors and the upcoming QX9775, really show this to be a dual-processor workstation centric product — only the big money spenders need apply here.

The Tylersburg platform is going to be built for Nehalem and will not feature a memory controller on it, at least not according to these diagrams.  Both of these chipsets will support PCIe 2.0 of course and the new Intel ICH10 (features on it are a mystery).  The differentiation point here is that the top solution supports two QPI connections while the DT chipset will only have one.

More detail on these new upcoming chipsets is seen in the block diagrams above.  The Intel 5400 (previously known as Seaburg) will support 32 PCIe 1.0 lanes and each set of 16 will run to an nForce-100 MCP that will in turn create two of its own PCIe 1.0 x16 slots.  These four slots will be used for multi-GPU graphics on the Skulltrail platform and will be the first non-NVIDIA chipset to actually support the SLI feature.

The memory controller on the 5400 chipset was showing support for FB-DIMM 1066 MHz support in the first roadmap but this block diagram only indicates support 800 MHz clock speeds.

The Tylersburg chipset scheduled for Q4 of next year is much more interesting – the first implementation of Intel’s Quick Path Interconnect is at work.  Though a DP setup is demonstrated above, the single CPU chipset will have one less CPU socket (duh).  Intel could offer a version for SP systems with the same dual 36D IOH chipsets for quad graphics or a single chipset for dual graphics slots.

Notice as well that the Gainestown CPUs (and thus Bloomfield as well) are showing a three channel memory system where each channel can support three DIMMs of DDR3-1333 memory.  This should be an amazingly fast memory subsystem leading to new highs in terms of raw memory bandwidth and lower latencies.  A sad note is that the ICH9 continues to stick around, connected by a legacy bus to the Tylersburg chipset.

Conclusions

It doesn’t seem all that long ago that Intel’s move from the P4 NetBurst architecture to the Core Architecture was what we were looking forward to, and now we are anticipating Intel’s next major architecture shift to Nehalem.  The move an integrated memory controller and new interconnect aren’t gimmes though and Intel is going to have to prove the architecture can work and be accepted at the same level Core has been.  As the other major player in the CPU world knows, better technology doesn’t always equal better products.