Since these Dunnington processors are still based on Penryn, they will continue to use a front-side bus, labeled as 1066 MHz in the slide from Sun, but hopefully that’s an oversight. They will run on the existing Clarksboro chipset and use the mPGA 604 pin socket, making them compatible with existing Xeon Tigerton processors. The TDP of Dunnington is listed as 130 watts, signaling that clock speeds will be somewhat lower than the 3.0 GHz we are currently seeing on quad-core parts that hae 150 watt TDPs.
These are due out in the second half of this year.
For more information (a re-hash of news about Nehalem) and estimated performance numbers, visit the Dailytech article here.
Dunnington includes 16MB of L3 cache shared by all six processors. Each pair of cores can also access 3MB of local L2 cache. The end result is a design very similar to the AMD Barcelona quad-core processor; however, each Barcelona core contains 512KB L2 cache, whereas Dunnington cores share L2 cache in pairs.
To sweeten the deal, all Dunnington processors will be pin-compatible with Intel Tigerton processors, and work with the existing Clarksboro chipset. Intel’s slide claims this processor will launch in the second half of 2008 — a figure consistent with previous roadmaps from the company.
The leaked slide deck also includes more information about Intel’s Penryn successor, codenamed Nehalem. Nehalem is everything Penryn is — 45nm, SSE4, quad-core — and then some. For starters, Intel will abandon the front-side bus model in favor of QuickPath Interconnect; a serial bus similar to HyperTransport.