This is still very good news and if Intel can pump out the new architecture at these frequencies the majority of our doubt about Intel’s execution of Nehalem would likely be quelled.
The first available Nehalemprocessors will be built on the existing 45nm manufacturing process, will incorporate SSE4 instructions, and will feature four fully integrated cores. Each core will have its own dedicated 256KB L2 cache and each core will share an 8MB of L3 cache pool. The bulk of these 731 million transistor processors are dedicated to cache.
Event demonstrations at the Shanghai Intel Developer Forum, occurring now until the end of the week, show A1 silicon Bloomfield-based Nehalemprocessors at IDF at a speedy 3.2 GHz.
Like the 533 MHz variants of Intel’s new Silverthorne-based Atom processors, Nehalem will also incorporate Simultaneous Multithreading (SMT) which is also known as Hyper-Threading (HT). Each physical core in a single Nehalem processor is paired up with its own virtual core. As a result, the processor is treated as having eight threads/processors.
