Nehalem Power Management
Up until now, everything we have discussed about Nehalem has really been information available prior to last week. What had still been a mystery was the secrets of the power consumption and regulation logic in the processor.
What Intel revealed was actually a bit more surprising than expected. Rather than some simple algorithms for switching off the power planes of the new Nehalem cores, the Core i7 will feature a complete microcontroller dubbed the PCU – power control unit. This section of the CPU actually consists of more than a million transistors, more than the entirety of the Intel 386 processor! This new controller is responsible for managing the power states of the processing cores based on load using real-time sensors for temperature, current and power. In fact, the new PCU is a firmware item rather than dedicated hardware indicating that it could be updated and changed throughout the life of the processor.
The Nehalem core also has a new trick in its bag that enables it to lower the power consumption of a core to nearly 0 watts – something that wasn’t possible on previous designs. You can see in the image above what the total power consumption of a core was typically made up of with the Core 2 series of processors – clocks and logic are the majority of it yes, but a third or more is related to leakage of the transistors and was something that couldn’t be turned off in prior designs.
Intel provided a quick walk through of how a Core 2’s power states will compare to Nehalem’s – this first set is for the existing Core 2 products. When active, the core is using 100% of its power (or at least most of it if the clock rate is reduced).
When C1 and C2 are initialized the primary core pipelines are stopped as are most of the clock themselves. The distributors and leakage power remains though.
In the mid-90s Intel developed the C3 state that was able to stop all clock generation.
And then in the 2000s Intel developed C4, C5 and C6 that all were steps in reducing the leakage voltage by lowering the Vcore. This Vcore reduction was done over a shared voltage plane though meaning that if one core wanted to power down it had to wait for all cores to become idle.
Here is a diagram of how the Core 2 CPUs worked this over time. You can see that early on in the graph Core 1 goes “idle” since it has no more work to crunch on. Core 0 is still chugging away though so the lowest power state that Core 1 can reach is C3. Once Core 0 is ready to idle down it and Core 1 can both reach C6 states lowering the power consumption significantly. However, if Core 1 is then assigned new work by the operating system, it must turn on its clocks and thus BOTH cores are required return to at least the C3 state.
How is this changed with Nehalem? Well with the independent power controller in the PCU and the different power planes that each core rests on, the power consumption for each core is completely independent from the others. You can see in this diagram that though Core 3 is loaded the entire time, both Core 2 and Core 0 are able to power down to practically 0 watts when their work load is complete.
This of course leads to better core efficiency on the new Nehalem processors but there is another part that needs to be discussed – the “uncore” as Intel puts it; that requires power too.
This of course leads to better core efficiency on the new Nehalem processors but there is another part that needs to be discussed – the “uncore” as Intel puts it; that requires power too.
While our first section focused on the cores and their power consumption, there are many other segments of Nehalem that require power including the uncore logic, IO, uncore clock distribution and leakage. These operate completely separate from the cores of the CPU thank in part to the modular design that Intel has built.
How do these sections work into the picture of power consumption? At C6 states the uncore can power down significantly including the logic blocks and IO. However, it is interesting to note that the uncore doesn’t scale in power with the cores themselves since even if just one core is loaded the L3 cache, memory controller an QPI interfaces must be functioning. It is because of the new uncore features that did not exist in the previous CPU design that I wonder if idle power consumption numbers can actually be lower with Nehalem.
