The Process Tech
AMD’s Fab 36 and Fab 38 (formerly Fab 30) make up the backbone of GLOBALFOUNDRIES.  Fab 36 was built from scratch as a 300 mm wafer facility using the 90 nm node and eventually transitioning to 65 nm and now 45 nm.  Fab 38 is a totally reworked Fab 30 which will support 300 mm wafers as well.  Fab 36 will be used for the high performance SOI wafers being used for AMD’s processors, while Fab 38 will be retooled to handle bulk silicon.

Currently GLOBALFOUNDRIES is only producing the 45 nm SOI parts, and from all indications it may not open up that manufacturing to other companies.  Questions are still unanswered about this, but it could simply be that SOI is specialized enough that only a handful of companies would find it useful for their products.  Or it simply could be that no other company has a ready to fab part that can utilize SOI on 45 nm design rules.

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While AMD/GF have not always had the first implementations of these technologies in the world, they have continued to be leading edge due to their intelligent partnerships with other technology leaders around the world.

GLOBALFOUNDRIES expects their upcoming 32 nm product lines to be the first ones opened to other parties.  GF is currently expecting to take designs based on both bulk and SOI processes at the end of 2009, with initial production in Q1 or early Q2 of 2010.

The most advanced process to date for 3rd party foundry work is that of TSMC’s 40 nm, which saw its first major introduction with the AMD Radeon HD 4770, based on the RV740 chip.  Rumors have been circulating for quite some time that the 40 nm process is…problematic.  While it features very small geometries, it apparently is quite leaky and yields are poor.  So while it is more power efficient than TSMC’s previous 55 nm process, it leaves much to be desired.  GLOBALFOUNDRIES sees a wide open field when it comes to process technology and quality, and it feels that it will have a 32 nm product that will not exhibit the problems that the TSMC 40 nm process has.

GLOBALFOUNDRIES has at its fingertips the advanced lithography and materials technology needed to open up a bulk 32 nm process which should be industry leading in overall yields, overall efficiency, and overall transistor switching performance.

Immersion lithography is the first step, and GLOBALFOUNDRIES has perfected it in mass production with the AMD Phenom II series of processors.  This allows for smaller and more accurate photo lithography, which in turn leads to more accurate etching of the silicon.  This means fewer potential defects caused by a misbehaved light wave.  Higher accuracy also leads to greater performance and efficiency, as the distance between features in the design is more consistent.

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A good description of the first three product lines that GF will be offering to partners at the 32 nm node.  Due to APM, there can be some further customization of these base processes, depending on the customer.

Material science makes up the largest portion of money typically spent on process technology.  While optics is a close second, cheating light is sometimes a lot easier than cheating material physics.  We can see from the TSMC 40 nm example that they have the optics down, but the materials for producing these parts is lacking considering the geometries involved.  AMD introduced Low-K dielectrics with its 130 nm process, using the Black Diamond product.  At 65 nm AMD used IBM’s Low-K film, and continues to use it in the current 45 nm process.  This low-k material acts as a more effective insulator on the chip, thereby decreasing leakage and improving efficiency.  GLOBALFOUNDRIES’ 32 nm process will introduce Ultra Low-K materials.  Low-K has a k value of 3.0, while Ultra Low-K has a k value of 2.4, which is an improvement of 20% (lower is better).

Ultra Low-K is not the only new twist to these upcoming 32 nm process.  High K Metal Gates will enhance electron mobility, and decrease resistance.  Currently Intel uses High-K in their 45 nm parts, and AMD will obviously be utilizing it in their 32 nm SOI parts.  This again improves efficiency and transistor switching performance.

GLOBALFOUNDRIES also has a lot of expertise in both compressive and expansive strain.  Currently the 45 nm process utilizes DSL (dual strain layer) to manipulate the silicon by either making it denser or thinner, depending on the desired properties of the transistor design.

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