Sandy Bridge engineering sample (photo courtesy of Coolaler).
Sandy Bridge is going to be a 32 nm product with 32K of L1 data and 32K of L1 instruction cache, 256 KB of L2 cache per core, and a nice 6 MB of L3 cache to be shared around the native four core design. The sample in question is running at a unimpressive 2.5 GHz, but this is not surprising considering it is an early engineering sample. Clockspeeds will obviously be increased substantially when the product is released to desktops in late Q4 2010 or Q1 2011. The integrated graphics portion is a complete mystery though, but considering the big leap that Intel made with Clarkdale’s integrated graphics, this area could have received much needed attention and a jump up to DX 11 standards. Rumors have it that many of the former Larrabee staff were transferred to the integrated graphics design teams, and hopefully we should see a product which will at least come close to AMD’s Fusion products in terms of graphical performance and functionality.
The tests run on this sample were fairly limited, and what little we could gather is that Sandy Bridge does improve upon the performance per clock of Nehalem, but it does not blow it out of the water. I believe that right now Intel has extracted about as much performance from a X86 CPU as they possibly can, considering the manufacturing technology of today. Certainly in the future more performance can be extracted due to relaxed transistor budgets afforded by smaller processes, as well as clockspeed increases and improvements in cache transistor designs that will be released in coming years. This at least creates and opening for AMD to potentially match Intel in terms of per clock performance with their upcoming Bulldozer core, but I certainly do not expect AMD to take any kind of performance lead in most applications. About the only two areas where AMD could potentially score big is in integer limited performance, where their cluster based SMP (two ALU units per core) may outperform what Intel has to offer, and if AMD can get much more software support for their “APU” concept which would leverage the integrated graphics core as a massively parallel floating point and streaming unit.
Still, Intel is in a far superior position, as this will be their second architecture on a 32 nm process. AMD has yet to release any 32 nm parts, and we have only seen a publicly shown sample of the Ontario APU, which is the low power variant (Bobcat) of their Fusion platform. And that particular sample was reportedly fabricated on TSMC’s 40 nm process. 32 nm Llanos are sampling with partners, but this quad core Phenom II variant certainly will not turn heads in terms of per clock performance compared to Sandy Bridge. The saving grace for this particular part could very well be the integrated graphics portion, which is going to be very well supported by AMD and their Catalyst driver program due to its design being essentially lifted from the HD 5000 series of graphics chips.
Remember as well that this is an engineering sample, and we do not know what kind of turbo boost we will see in clockspeeds, as well as how it handles individual core speeds depending on loads. It could be another step up from the current Nehalem designs, and thereby increase overall performance across multiple applications (far greater than what we see from this 2.5 GHz clocked core). Intel could also have disabled some advanced functionality in these engineering samples, which would again decrease overall performance as compared to a final, shipping product. But from what we see so far, Sandy Bridge will not disappoint in the traditional CPU market.