Nano DC: The Next Generation
VIA has not given up its hopes on creating and selling a compelling, affordable, and powerful (for its thermal envelope) CPU. In fact, the new push for powerful yet mobile devices has given new impetus to VIA to attempt to create a product that not only competes with the latest generation Intel Atom processors, but exceeds them in terms of performance per watt. VIA is in fact upping the ante by including this product with the latest VIA chipset, the VN1000, which features integrated graphics based on the Chrome 500 series architecture.
The VIA Nano has a relatively large 1 MB L2 cache, which is big for a low power processor. Note as well the encryption unit.
The Nano DC will be a 40 nm chip produced by TSMC. The current samples that reviewers have on hand are based on the older 65 nm process. As such the thermals and power draw of these samples are not going to be representative of the actual 40 nm products. The current single core 65 nm VIA Nano at 1.8 GHz has a 25 watt TDP. It is estimated that the 40 nm dual core version will also have a TDP of 25 watts at 1.8 GHz. So VIA essentially doubled the chip for the same clockspeed and power dissipation/draw.
The chip is relatively unchanged from the previous generation. All of the functional units are essentially identical to the Nano 3000 series (which includes SSE 4.1). What VIA did was just double the cores on a single die, and allow these cores to communicate with each other through the front side bus (much like the Intel Pentium 4 did, as well as the Core 2 Quad products). There obviously was more work done than this, but between porting the design to TSMC’s 40 nm process, and ensuring that the cores do in fact communicate as they should, it was about as simple a product migration as is possible.
The V4 FSB that VIA uses is a “proprietary” affair, which is essentially an Intel GTL+ bus with a few extra tweaks aimed at better communicating with VIA’s processor designs. This means that the VN1000 northbridge contains the memory controller and provides the means for the two cores to communicate with each other. It is feasible under heavy loads that the 800 MHz FSB could become saturated, but when we figure that the Nano is only running at 1.8 GHz, it is more than adequate for the needs of the processor.
The processor is still an out-of-order design, but with plenty of architectural tweaks to avoid inflating the die size or transistor count of the product. It is said that the last 10% of processor performance can take up to a 50% increase in transistor count. VIA is sacrificing that extra performance, and in so doing has made a very lean and mean processor design that can still compete with the industry at large. The CPU also supports 64 bit processing, so it is adept at both 32 bit and 64 bit operation.
The only communication between cores is handled through the front side bus.
The floating point/SSE unit for this chip is surprisingly robust. Apparently the folks at Centaur spent quite a bit of time on it, and have a very aggressive approach to this unit. In my testing the floating point and multi-media performance of this chip matched that of larger desktop CPUs at the same clockspeed. VIA also includes full virtualization support in this processor, which could be interesting if these products make an impact in the blade server market.
Power is a big issue with these products, and VIA has also implemented a very aggressive power saving routine. It now features the C6 state, which essentially powers down the entire processor when idle. The last big feature is that of the VIA Padlock. This is a pretty hefty engine that supports AES encryption up to 256 bit key sizes.
The Nano DC is certainly a serious product for its marketplace, and doubling the performance while keeping the same TDP is a big step for VIA. Unfortunately for VIA, the marketplace has not stood still and we see pretty solid Pineview based Atoms dominating. AMD is also about to unleash their native dual core Ontario and Zacate APUs.
