A while back, Intel and Micron jointly announced the beginnings of 20nm flash memory production, promising a 50% increase in die count per wafer (or a 50% reduction in per die production cost, depending on how you slice it). This shrink only did just that – shrink the die. Capacity remained at 64Gbit (8GB).
A few days ago IMFT also announced another way to shrink that die, but this time keeping with the now ‘old’ 25nm process. It turns out they have refined 25nm to the point where consumer-grade TLC flash can be produced. TLC is Triple-Level-Cell. While SLC (Single) holds 1 bit per cell, and MLC (Multi) holds two, TLC holds 3 bits per cell. Compared to the MLC 25nm dies, this gives a capacity increase without changing much else. IMFT, however, is happy with the 8GB ‘sweet spot’, so instead of jumping to a 12GB die of the same physical size, they are opting to instead shrink the current 25nm die to 131mm^2.
25nm TLC die, same 8GB capacity, but less area than the 25nm MLC die.
This gives Intel and Micron two options for ultimately reducing the price of flash – either by shrinking the process and getting more 8GB MLC dies out of a 20nm wafer, or by squeezing more bits into each cell of existing 25nm flash.
This is good stuff. Let’s hope it gets even more SSD’s into even more machines this holiday season.
3 bits per cell NAND is not
3 bits per cell NAND is not good enough for SSD for now.The leader in 3 bits per cell is Toshiba/Sandisk and they sell a lot of it but not for SSDs.