Fujitsu and SuVolta, a designer of custom CMOS chips, have announced the fruits of a recent joint project aimed at developing a 3-dimensional transistor to match Intel’s FinFET. As we have seen with Ivy Bridge, this advancement in transistor technology significantly reduces the power needs of a chip which utilizes them. The current prototypes utilize a 65nm process but the companies claim it will easily scale to 32nm. SemiAccurate also reports that the Deeply Depleted Channel shows an advantage over Intel’s Tri-gate transistor design as DDC is capable of handling variable threshold voltages; Intel’s requires that all threshold voltages match. It will be a while before we see these implemented at Fabs but it is nice to see competition in the next generation of transistor technology.
"During the IEDM conference in Los Altos earlier today Fujitsu presented a paper jointly authored by SuVolta. The paper describes how a newly developed transistor with a deeply depleted channel can achieve the same power savings as those announced by Intel that has launched a FinFET-transistor, which the company calls a 3D transistor."
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