We’ve just met Intel’s Tri-Gate transistor technology, which offers significant improvements in power efficiency as well as reducing waste hear but researchers have already moved onto the next new technology. Referred to as silicon nanowire transistors in this story at The Register, the next generation of transistor may have no gates whatsoever, or be made entirely of gates, depending on how you look at it. The wire will be wrapped in a silicon oxide, high-K metal gate making the transistor cylindrical and not limited in the number of gates possible in the same way that planar or 3D transistors are. The development of this technology is in its infancy but could well help us see chips go below 5nm as it matures.
"The next step in transistor architecture will likely be silicon nanowires – extremely thin silicon wires that will form the transistor’s chanel, surrounded on all sides by a wrap-around silicon oxide, high-K metal gate.
"It’s the ultimate fully-depleted device," the director of IBM’s Semiconductor Research & Development Center, Gary Patton, said during his keynote address at Wednesday’s Common Platform Technology Forum 2012 in Santa Clara, California. "You don’t have a gate on just two sides, or three sides – it’s fully encapsulating the silicon nanowire device."
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