In case you were worried that Intel was the only one successfully researching and implementing 3D transistors, this research from Hokkaido University in Sapporo will cheer you up. Whereas Intel went with 22nm process SOI high-K gates utilizing Hafnium, this process creates nanowires made of indium gallium arsenide at around 10nm, though the process does not necessarily translate directly. NanoTechWeb's article mentions that some of these transistors have 6 edges, which if all could be successfully utilized means a doubling of density compared to Intel's design, though they do not mention what the thermal impact of the increased gate count would be. It would seem that Intel is already aware and interested in this technology; for building CMOS chips as opposed to CPUs however.
"Gate structures in silicon-based transistors will have to evolve in the future as these devices become ever smaller. Researchers in Japan have made an important advance in developing these next-generation architectures by successfully fabricating vertical transistors from semiconducting nanowires on a silicon substrate. The wires, made from indium gallium arsenide, are surrounded by 3D – rather than planar-shaped – gates and the finished devices have extremely good electronic properties."
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