At the 2012 edition of the Intel Developer Forum, the company has revealed some new details about the Haswell architecture due out next year.
Ah, IDF – the Intel Developer Forum. Almost every year–while I sit in slightly uncomfortable chairs and stare at outdated and color washed projector screens–information is passed on about Intel's future architectures, products and technologies. Last year we learned the final details about Ivy Bridge, and this year we are getting the first details about Haswell, which is the first architecture designed by Intel from the ground up for servers, desktops, laptops, tablets and phones.
While Sandy Bridge and Ivy Bridge were really derivatives of prior designs and thought processes, the Haswell design is something completely different for the company. Yes, the microarchitecture of Haswell is still very similar to Sandy Bridge (SNB), but the differences are more philosophical rather than technological.
Intel's target is a converged core: a single design that is flexible enough to be utilized in mobility devices like tablets while also scaling to the performance levels required for workstations and servers. They retain the majority of the architecture design from Sandy Bridge and Ivy Bridge including the core design as well as the key features that make Intel's parts unique: HyperThreading, Intel Turbo Boost, and the ring interconnect.
The three pillars that Intel wanted to address with Haswell were performance, modularity, and power innovations. Each of these has its own key goals including improving performance of legacy code (existing), and having the ability to extract greater parallelism with less coding work for developers.
The modularity of Haswell is what gives the processor design its extreme flexibility while providing a consistent optimization path for software developers. The ability for a designer to write an application that can run (though at different feature or performance levels) across the entire array of devices that Haswell will find its way in is powerful.
Haswell (at least in this iteration) will be available in various different configurations including 2-4 processing cores, three different levels of graphics subsystem, differing idle and active power levels, interconnects, and platforms. This will greatly increase the power and performance ranges of Haswell compared to Ivy Bridge (and Sandy Bridge) and is enabled by the system agent that acts as the intermediary between all of the components on the SoC.
Intel also claims that Haswell will permit third-party IP integration, and thus will be capable of adding specific features and technologies as the OEMs demand.
Changes to power management on Haswell address both active (in use) and sleep states in order to see the biggest alterations from previous architectures. The goal is to lower the power consumption required during CPU load while also decreasing the amount of time it takes for the entire system to enter and leave sleep states. Intel introduces a new S0ix status that it is borrowing from the ultra-mobile designs of Atom to get a 20x improvement in low power states, and allows improved realizable battery life.
Just as important as the new states themselves is that Intel claims they are completely transparent to "well written" software – which is a designation I haven't yet gotten a clarification on.
Other changes in the design address power with Haswell, including changes to Turbo Boost technology and more granular voltage and frequency "islands" for the CPU to enter. Also changed from SNB and IVB is that the frequency of the cores is decoupled from the ring bus allowing voltages to scale more gracefully to where the power is actually needed. For example, Ivy Bridge and Sandy Bridge both required power to increase on the CPU cores when the GPU needed more bandwidth on the ring interconnect for other purposes, which is a waste of valuable power.
While we talked about the idle power changes in the slide above, Intel also pointed out that at this point that is is the only CPU vendor that has complete control over its manufacturing. Intel can utilize that advantage by tweaking the process in very specific ways to meet any goals that the engineers might have.
Because the majority of Haswell designs will be completely Intel-based platforms, it makes sense for Intel to address this as well. You will see new voltage regulators and better power-managed controllers (embedded now) in addition to new IO options like I2C, SDIO and I2s that are traditionally only found in mobile devices. New link power states for traditional IO connections like USB and SATA are being introduced that can nearly drop power draw at idle to zero watts.