SOI has been around for some time now, but in partially depleted form (PD-SOI). Quite a few manufacturers have utilized PD-SOI for their products, such as AMD and IBM (probably the two largest producers of SOI based parts). Oddly enough, Intel has shunned SOI wafers altogether. One would expect Intel to spare no expense to have the fastest semiconductor based chips on the market, but SOI did not provide enough advantages for the chip behemoth to outweigh the nearly 10% increase in wafer and production costs. There were certainly quite a few interesting properties to PD-SOI, but Intel was able to find ways around bulk silicon’s limitations. These non-SOI improvements include stress and strain, low-K dialectrics, high-K metal gates, and now 3D FinFET Technology. Intel simply did not need SOI to achieve the performance they were looking for while still using bulk silicon wafers.
Things started looking a bit grim for SOI as a technology a few years back. AMD was starting to back out of utilizing SOI for sub-32 nm products, and IBM was slowly shifting away from producing chips based on their Power technology. PD-SOI’s days seemed numbered. And they are. That is ok though, as the technology will see a massive uptake with the introduction of Fully Depleted SOI wafers. I will not go into the technology in full right now, but expect another article further into the future. I mentioned in a tweet some days ago that in manufacturing, materials are still king. This looks to hold true with FD-SOI.
Intel had to utilize 3D FinFETs on 22 nm because they simply could not get the performance out of bulk silicon and planar structures. There are advantages and disadvantages to these structures. The advantage is that better power characteristics can be attained without using exotic materials all the while keeping bins high, but the disadvantage is the increased complexity of wafer production with such structures. It is arguable that the increase in complexity completely offsets the price premium of a SOI based solution. We have also seen with the Intel process that while power consumption is decreased as compared to the previous 32 nm process, the switching performance vs. power consumption is certainly not optimal. Hence the reason why we have not seen Intel release Ivy Bridge parts that are clocked significantly faster than last generation Sandy Bridge chips.
FD-SOI and planar structures at 22 nm and 20 nm promise the improve power characteristics as compared to bulk/FinFET. It also looks to improve overall power vs. clockspeed as compared to bulk/FinFET. In a nutshell this means better power consumption as well as a jump in clockspeed as compared to previous generations. Gate first designs using FD-SOI could be very good, but industry analysts say that gate last designs could be “spectacular”.
So what does this have to do with ST Ericsson? They are one of the first companies to show a products based on 28 nm FD-SOI technology. The ARM based NovaThore L8580 is a dual Cortex A9 design with the graphics portion being the IMG SGX544. At first glance we would think that ST is behind the ball, as other manufacturers are releasing Cortex A15 parts which improve IPC by a significant amount. Then we start digging into the details.
The fastest Cortex A9 designs that we have seen so far have been clocked around 1.5 GHz. The L8580 can be clocked up to 2.5 GHz. Whatever IPC improvements we see with A15 are soon washed away by the sheer clockspeed advantage that the L8580 has. While it has been rumored that the Tegra 4 will be clocked up to 2 GHz in tablet form, ST is able to get the L8580 to 2.5 GHz in a smartphone. NVIDIA utilizes a 5th core to improve low power performance, but ST was able to get their chip to run at 0.6v in low power mode. This decrease in complexity combined with what appears to be outstanding electrical and thermal characteristics makes this a very interesting device.
The Cortex A9 cores are not the only ones to see an improvement in clockspeed and power consumption. The well known and extensively used SGX544 graphics portion runs at 600 MHz in a handheld device, and is around 20% faster clocked than other comparable parts.
When we add all these things together we have a product that appears to be head and shoulders above current parts from Qualcomm and Samsung. It also appears that these parts are comparable, if not slightly ahead, of the announced next generation of parts from the Cortex A15 crowd. It stands to reason that ST Ericsson will run away with the market and be included in every new handheld sold from now until the first 22/20 nm parts are released? Unfortunately for ST Ericsson, this is not the case. If there was an Achilles Heel to the L8580 it is that of production capabilities. ST Ericsson started production on FD-SOI wafers this past spring, but it was processing hundreds of wafers a month vs. the thousands that are required for full scale production. We can assume that ST Ericsson has improved this situation, but they are not exactly a powerhouse when it comes to manufacturing prowess. They simply do not seem to have the FD-SOI production capabilities to handle orders from more than a handful of cellphone and table manufacturers.
ST Ericsson has a very interesting part, and it certainly looks to prove the capabilities of FD-SOI when compared to competing products being produced on bulk silicon. The Nova Thor L8580 will gain some new customers with its combination of performance and power characteristics, even though it is using the “older” Cortex A9 design. FD-SOI has certainly caught the industrys’ attention. There are more FD-SOI factoids floating around that I want to cover soon, but these will have to wait. For the time being ST Ericsson is on the cutting edge when it comes to SOI and their proof of concept L8580 seems to have exceeded expectations.