Hybrid Memory Cubes are DRAM stacked in layers with logic on the bottom layer to decide which memory layer to address commands to whic is being developed by a team that includes Altera, ARM, IBM, SK Hynix, Micron, Open-Silicon, Samsung and Xilinix. This is intended to give DRAM enhanced parallelization which will help it keep up with today’s multi-cored processors. Micron's example which the Register takes a look at here claims up to 10 GB/sec (80 Gb/sec) of bandwidth from each of the 16 vaults present on the chip, a vault being an area of memory on a layer. That compares favourably to the maximum theoretical JEDEC speed of DDR3-1333 which is just a hair over 10GB/s. Read more here.
"Dratted multi-core CPUs. DRAM is running into a bandwidth problem. More powerful CPUs has meant that more cores are trying to access a server’s memory and the bandwidth is running out.
One solution is to stack DRAM in layers above a logic base layer and increase access speed to the resulting hybrid memory cubes (HMC), and Micron has done just that."
Here is some more Tech News from around the web:
- Prolonged Ivy Bridge life-cycle affects Intel 2014 CPU roadmap @ DigiTimes
- Repairing Dead USB Flash Drives @ Hack a Day
- Globalfoundries gearing up for high-volume MEMS manufacturing @ DigiTimes
- Gigabyte expected to post 28-year shipments high of 21 million motherboards in 2013 @ DigiTimes
- THOUSANDS of Ruby on Rails sites leave logins lying around @ The Register
- How to Remote Control Your Camera with Darktable on Linux @ Linux.com
While I get that the stacking
While I get that the stacking improves density and increases parallelisation , how is this stack connected to the CPU ?
My understanding is that memory BW is limited by the interface between memory controller on die and the memory module via the motherboard – i.e JEDEC DDR spec . How does this solution overcome this ?
Is the memory stack going to be soldered onto the processor die or PCB ? or is it slot module like present ?
Some clarification please . THNX
Stacked – but it’s all
Stacked – but it’s all silicon