Introduction and Background
Intel invited press to its Folsom offices to see how SSDs are tested and validated to give us a sense of solid state reliability.
Back in 2010, Intel threw a bit of a press thing for a short list of analysts and reviewers out at their IMFT flash memory plant at Lehi, Utah. The theme and message of that event was to announce 25nm flash entering mass production. A few years have passed, and 25nm flash is fairly ubiquitous, with 20nm rapidly gaining as IMFT scales production even higher with the smaller process. Last week, Intel threw a similar event, but instead of showing off a die shrink or even announcing a new enthusiast SSD, they chose to take a step back and brief us on the various design, engineering, and validation testing of their flash storage product lines.
At the Lehi event, I did my best to make off with a 25nm wafer.
Many topics were covered at this new event at the Intel campus at Folsom, CA, and over the coming weeks we will be filling you in on many of them as we take the necessary time to digest the fire hose of intel (pun intended) that we received. Today I'm going to lay out one of the more impressive things I saw at the briefings, and that is the process Intel goes through to ensure their products are among the most solid and reliable in the industry.
The next page will go into some of the gory details (and cool pics!), but first a bit of background. The base of Intel's development cycle is based on a set of developmental actions all taking place in parallel:
Starting from the bottom is the silicon layer. This is the nose-to-the-grindstone work of designing the actual flash die components, producing wafers of sufficient yield to meet the market demands, and engineering the mechanisms that enable the flash to endure even in the face of die shrinks and cell voltage shifts over time.
Next up is the system layer. This group handles the physical design of the SSDs, as well as the NAND die packaging (stacking). Firmware is included in this mix, and at this layer the firmware aids in NAND longevity by handling the necessary wear leveling mechanisms that prevent the host system from hammering on a single area of flash, which would cause it to wear out prematurely.
At the top is the actual testing, which the remainder of this article will focus on. This process involves taking the finished product and testing it in the actual environments it is likely to be installed. This process also includes JEDEC standards testing (excellent explanation / presentation at this link) and validating that a given product line can perform at the rated temperature and vibration specs. These are the things that play into ensuring the products will live up to their stated warranty.
All of this testing applies, with varying degrees of validation testing, to all of the Intel flash storage product lines:
Products are validated more thoroughly and heavily as you work your way up from consumer to data center lines. This makes sense, as a data center product is rated for far heavier workloads than a consumer product.