You know the PCI-SIG might break the pattern with PCIe 5.0, just to mess with us. But for right now, Tom's Hardware seems to have acquired part of the PCIe 4.0 spec and it is expected to get 2 GB/s bandwidth per lane, per direction. This is double the bandwidth of PCIe 3.0, continuing the trend of each major PCIe release doubling bandwidth of the previous major version.
A 16-lane PCIe 4.0-compliant graphics card or storage add-in board (that feels so weird to write…) has a maximum bandwidth of 32 GB/s inbound and 32 GB/s outbound, 64 GB/s total. This is still below GDDR5 bandwidth, but approaching the same order of magnitude. That said, memory bandwidth is the major roadblock for optimizing GPGPU workloads, already. APUs will probably still have an advantage in CPU and GPU tag-teaming tasks, despite their lower compute performance.
According to bit-tech, the spec is expected to arrive with Skylake and its 100-series chipset.