Need more NAND? Just stack it vertically!

Samsung has certainly been pushing the envelope in the SSD field. For the past two years straight, they have launched class leading storage products, frequently showing outside-the-box thinking. Their 840 PRO series was an impressive MLC performer to say the least, but even more impressive was the 840 EVO, which combined cost-efficient TLC flash with a super-fast SLC cache. The generous SLC area, present on each die and distributed amongst all flash chips within the drive, enabled the EVO to maintain PRO-level performance for the majority of typical consumer (and even power user) usage scenarios. The main win for the EVO was the fact that it could be produced at a much lower cost, and since its release, we've seen the EVO spearheading the push to lower cost SSDs.

All of these innovations might make you wonder what could possibly be next. Today I have that answer:

If you're going "Hey, they just changed the label from 840 to 850!", well, think again. This SSD might have the same MEX controller as its predecessor, but Samsung has done some significant overhauling of the flash memory itself. Allow me to demonstrate.

Here's standard (2D) flash memory, where the charge is stored on a horizontal plane:

..and now for 3D:

The charges (bits) are not stored at the top layer. They are stored within all of those smaller, thinner layers below it. You're still looking at a 2D plane (your display), so here's a better view:

Here's an evolution of old to new:

The newer type of flash (second from left) is called Charge Trap Flash. It hadn't really caught on in the 2D world, but it works extremely well with the particular process Samsung has chosen.

Building chips in this fashion is not exactly easy. Stacking a bunch of layers is not that big of a deal, but then etching deep holes through all layers, and then applying coatings from the inside-out, is a novel idea to say the least.

The trick up Samsung's sleeve is that since they are stacking vertically, they don't need to pack things in so tightly on the horizontal plane. This enabled Samsung to take a step back on the lithography side of things, meaning V-NAND is made on a 30nm process. Note the above slide was from the first generation of mass produced V-NAND that appeared only in one of Samsung's prior enterprise products. That 24-layer V-NAND had 128Gbit per die, which is comparable to current gen 20nm planar NAND. This newer 32-layer V-NAND is made with a smaller die capacity of ~86Gbit, presumably because yields are tougher the more layers you add. This is no biggie, though, as the smaller die footpront helps Samsung fit more dies in a chip package, compensating for the difference. Smaller dies also translates to more dies per wafer. Despite the lower die capacity, this rearrangement should yield a net benefit in manufacturing cost.

Whew, that was a lot of tech talk. For those who have stuck with me through it all, I reward you with a video illustrating how it's done:

If that's not out-of-the-box thinking, I don't know what is! Now let's see how this puppy does in the benches!

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