Coming in 2014: Intel Core M

Intel spent some time with us explaining its move to Broadwell and the 14nm process technology.

The era of Broadwell begins in late 2014 and based on what Intel has disclosed to us today, the processor architecture appears to be impressive in nearly every aspect. Coming off the success of the Haswell design in 2013 built on 22nm, the Broadwell-Y architecture will not only be the first to market with a new microarchitecture, but will be the flagship product on Intel’s new 14nm tri-gate process technology.

The Intel Core M processor, as Broadwell-Y has been dubbed, includes impressive technological improvements over previous low power Intel processors that result in lower power, thinner form factors, and longer battery life designs. Broadwell-Y will stretch into even lower TDPs enabling 9mm or small fanless designs that maintain current battery lifespans. A new 2nd generation FIVR with modified power delivery design allows for even thinner packaging and a wider range of dynamic frequencies than before. And of course, along with the shift comes an updated converged core design and improved graphics performance.

All of these changes are in service to what Intel claims is a re-invention of the notebook. Compared to 2010 when the company introduced the original Intel Core processor, thus redirecting Intel’s direction almost completely, Intel Core M and the Broadwell-Y changes will allow for some dramatic platform changes.

Notebook thickness will go from 26mm (~1.02 inches) down to a small as 7mm (~0.27 inches) as Intel has proven with its Llama Mountain reference platform. Reductions in total thermal dissipation of 4x while improving core performance by 2x and graphics performance by 7x are something no other company has been able to do over the same time span. And in the end, one of the most important features for the consumer, is getting double the useful battery life with a smaller (and lighter) battery required for it.

But these kinds of advancements just don’t happen by chance – ask any other semiconductor company that is either trying to keep ahead of or catch up to Intel. It takes countless engineers and endless hours to build a platform like this. Today Intel is sharing some key details on how it was able to make this jump including the move to a 14nm FinFET / tri-gate transistor technology and impressive packaging and core design changes to the Broadwell architecture.

Intel 14nm Technology Advancement

Intel consistently creates and builds the most impressive manufacturing and production processes in the world and it has helped it maintain a market leadership over rivals in the CPU space. It is also one of the key tenants that Intel hopes will help them deliver on the world of mobile including tablets and smartphones. At the 22nm node Intel was the first offer 3D transistors, what they called tri-gate and others refer to as FinFET. By focusing on power consumption rather than top level performance Intel was able to build the Haswell design (as well as Silvermont for the Atom line) with impressive performance and power scaling, allowing thinner and less power hungry designs than with previous generations. Some enthusiasts might think that Intel has done this at the expense of high performance components, and there is some truth to that. But Intel believes that by committing to this space it builds the best future for the company.

As explained to us by Sanjay Natarajan, VP and Director of 14nm Technology Development, the jump from 22nm to 14nm is not as simple as it might first appear. There are several measurements of transistor construction that can be modified when moving to a 3D design. The fin pitch is the measurement between peaks and has been lowered from 60nm to 42nm, a scaling rate of 0.7x. Intel was able to constrict the fins a bit more to allow for more current performance while reducing the number of fins for improvements in density and lower capacitance.

Intel Core M Processor: Broadwell Architecture and 14nm Process Reveal - Processors  1

Interestingly, Intel commented on the issue of the 14nm naming for this process in that no single pitch measurement shown to us was at 14nm. Instead, starting with the 90nm process design, no silicon manufacturer uses a node name that accurate reflects a specific pitch density and instead we are simply seeing a naming convention at work. Intel is basing the 14nm name on the 0.65x scaling rate seen with the combination of pitch adjustments on the tri-gate design, thus going from 22nm to 14nm is a 0.65x scaling rate. When pushed on if this represents the minimum drawable size of the technology, Intel declined to claim that was the case.

As an example implementation with this process change Intel showed an SRAM memory cell that shrunk from 0.108 um^2 at 22nm down to 0.058 um^2 on 14nm technology. That results in an area scaling rate of 0.54x.

The 14nm process technology provides improved performance and leakage and based on this graphic allows Intel to continue pushing forward with existing markets while addressing new ones. While maintaining the same leakage levels as previous process nodes Intel should be able to improve clock speeds for products in server computing and enthusiast designs. Client and mobile computing will see dual advantage of some slightly higher clock speeds (or maintained clock speeds with higher IPC) but also drop in leakage power allowing for longer battery life and new system designs. Most importantly, down into the 0.001x leakage levels Intel continues to push for 14nm to pave the way into the smartphone markets.

The key benefit across the board is performance per watt and Intel claims that the 14nm tri-gate process allows Broadwell-Y to see a 2x improvement over Haswell-Y in that field. The 2nd generation tri-gate transistors with better scaling at lower voltages along with the better than normal area scaling provided by this process shift help make this happen. But a lot of work was also done by the architecture design team working hand in hand with the process team to optimize the core for dynamic capacitance reductions (clock cycle switches).

Logic area is the combined area of gate pitch and metal pitch and this has been scaling at the rate of 0.53x since the 45nm process used on the Core 2 processor, allowing for more densely packed transistors. Interestingly, according to Intel, competing foundries have actually been a bit better over time in the density measurement but at the expense of being noticeably later in release. Just think back to the 40nm/45nm days as well as the current state of 22nm/20nm technologies out in the market to see this as being the case.

This time though it looks like Intel might be bypassing the competition in both timing and density, based on papers published by TSMC and the IBM Alliance. While GlobalFoundries and TSMC continue to attempt shipping their first FinFET designs in the market Intel has nearly ready to put products on the shelves based on its second generation of FinFET design. This is good news for Intel and associated products but is bad news for all other competing solutions that are dependent on third-part manufacturing.

Though the company clearly wasn’t going to be quoted with yield levels of 14nm wafers, Intel says that 14nm product is in a “healthy range” and has improvements coming down the line, just as they did with the 22nm process. The simple graphic above indicates that 14nm is slightly below where 22nm was this point, but that isn’t a surprise to those working on the platform. Intel is confident that they will be able to bring 14nm in line with the results seen with 22nm production which is actually Intel’s highest ever yield after tweaks and changes after implementation.

Both the process and the lead product (Broadwell-Y) have been qualified and are in volume production, shipping product to customers with a target release of holiday 2014.

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