AMD, in cooperation with Aricent and Mentor Graphics, recently demonstrated the first ARM-based Network Functions Virtualization (NFV) solution at ARM TechCon. The demonstration employed AMD's Embedded R-Series "Hierofalcon" SoC virtualizing a Mobile Packet Core running subscriber calls. The 64-bit ARM chip is now sampling to customers and will be generally available in the first half of next year (1H 2015). The AMD NFV Reference Solution is aimed at telecoms for use in communications network backbones where AMD believes an ARM solution will offer reduced costs (both initial and operational) and increased network bandwidth.
The NFV demonstration of the Mobile Packet Core entailed virtualizing a Packet Data Network Gateway, Serving Gateway, Mobility Management Entity, and virtualized Wireless Evolved Packet Core (vEPC) applications. AMD further demonstrated live traffic migration between ARM-based Embedded-R and x86-based second generation R-Series APU solutions. NFV is related to, but independent of, software defined networking (SDN). Network Functions Virtualization is essentially the virtualizing of network appliances with specific functions and performing those functions virtually using generic servers. For example, NFV can virtualize firewalls, gateways, load balancers, intrusion detection, DNS, NAT, and caching functions. NFV virtualizes the upper networking layers (layers 4-7) and can allow virtual tunnels through a network that can then be assigned functions (such as those listed above) on a per-VM or per flow basis. NFV eliminates the need for specialized hardware appliances by virtualizing these functions on generic servers which have traditionally been exclusively x86 based. AMD is hoping to push ARM (and it's own ARM-based SoCs) into this market by touting even further capital expenditure and operational costs versus x86 (and, in turn, versus specialized hardware that serves the entire network whereas NFV can be more exactly provisioned).
It is an interesting take on a lucrative networking market which is dealing with 1.4 Zetabytes of global IP traffic per year. I'm interested to see if the telecoms and other enterprise network customers will bite and give AMD a slice of this pie on the low end and low power fronts.
AMD "Hierofalcon" Embedded R Series SoC
Hierofalcon is the code name for AMD's 64-bit SoC with ARM CPU cores intended for the embedded market. The SoC is a 15W to 30W chip featuring up to eight ARM Cortex-A57 CPU cores capable of hitting 2GHz, two 64-bit ECC capable DDR3 or DDR4 memory channels, 10Gb Ethernet, PCI-E 3.0, ARM TrustZone, and a cryptographic security co-processor.The TechCon demonstration was also used to launch the AMD NFV Reference Solution which is compliant with OpenDataPlane platform. The reference platform includes a networking software stack from Aricent and an Embedded Linux OS and software tools (Sourcery CodeBench) from Mentor Graphics. The OpenDataPlane demonstration featured the above mentioned Evolved Packet Core application on the Hierofalcon 64-bit ARM SoC. Additionally, the x86-based R-Series APU, OpenStack, and Data Plane Development Kit all make up the company's NFV reference solution.