Since Samsung announced VNAND, we have been following its developments with great interest. You might have seen some of Andrew Walker's cool mock ups of what this new VNAND might look like:
Once a technology is released to the public, the only thing stopping you from knowing how it works is the ability to look inside. With detailed imagery of 32-layer VNAND recently released by TechInsights, not only was Andy able to conduct a very thorough analysis at his blog, we are able to get some incredibly detailed looks at just what makes this new flash memory tick:
Flash packaging, showing interconnect traces (which connect the outside of the package to the flash dies contained within).
1x: The 3D VNAND die itself. We'll use this as a point of reference of the magnification levels moving forward.
350x: This is the edge of the die, showing how the word (data) lines are connected to the individual layers.
1,500x: There it is, all 32 layers in all of their vertical glory. The only thing more amazing about the technology at play to create such a complex 3D structure at such a small scale, is the technology used to slice it in half (some of the material is tungsten) and take such a detailed 'picture' of that cross section.
30,000x: Finally, we have a top down slice of the channels themselves. This lets us get a good idea of the rough process node at play here. While the columns are 80nm in diameter, there are other features that are smaller, so the process itself still seemes to be in the ~40nm range.
Our focus is of course on the performance more than the extremeny low level bits, but it is definitely cool to see imagery of this new tech. For those curious, we encourage you to check out the detailed analysis done over at 3DInCities.
That’s one hell of a through
That’s one hell of a through silicon Via, now if we could just get some slices of more GPUs, and CPUs we could make out much better, than the blurred stuff that comes from chipworks(the non blurred images must cost a bundle). Hopefully adding more in the z axes, for flash storage, will give sufficient atoms to keep the TLC cells from loosing their state after long periods of inactivity, and keep any error correcting processing to a minimum, as the plainer dimensions continue to scale smaller in the X and Y. Hopefully there will be more SLC cache and MLC/TLC mixed on the newer SSDs, with controllers that can intelligently stage the data across the cache SLC portion, and the MLC/TLC main storage pools on the hybrid mix of flash cell types in some newer SSD lines. That’s one big stack of flash memory flap jacks! Now if the CPUs, and GPUs could get some tall orders of on DIE/Module RAM, stacked like this flash, that latency over PCI/other protocols could be further reduced.
That is some wicked
That is some wicked technology right there.
So after the “hybrid” HD
So after the “hybrid” HD should we call this an hydrid SSD ?
Thanks for showing this, it
Thanks for showing this, it gave perspective to what this technology is up close.