Further Power Saving Mechanisms

VAO, or “Voltage Adaptive Operation” was originally a technique introduced in Steamroller, but has been adapted for Carrizo.  It is common practice to apply more voltage to a CPU than is actually necessary, and this is done to prevent voltage droop.  Droop occurs when the core requires more power, but the voltage delivery system cannot support it that quickly.  Voltage drops, and if the CPU cannot handle it, then it will cause significant issues including crashing the machine.  By applying more voltage than necessary, then droops will never cross the threshold to cause problems.  The issue with this is that approximately 20% more voltage needs to be used to prevent droop.

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AMD has implemented VAO to get back some of those power savings.  When the processor detects when Vdd drops below the needed threshold, it will quickly respond by decreasing the operating frequency.  This keeps droop from causing problems by lowering the necessary voltage needed to run the processor.  Once Vdd recovers, then the processor increases the clockspeed back to the normal level.  Droop is relatively uncommon, happening around 1% or less of the time in a CPU under load.  Users will likely never notice the random drops in frequency.

This technology is applied to the GPU portion as well as the CPU.  The combination allows AMD to improve power consumption by around 20% for the CPU and an extra 10% for the GPU.  This is a big boost for battery life and a good reduction in heat production.  Droop was very problematic for a long time, especially considering all the extra power needed to overcome droop.

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Adaptive Voltage Frequency Scaling (AVFS) is a new way to monitor voltage and frequency across a chip.  Each Excavator core has 10 AVFS modules that have around 500 frequency sensing paths.  Modern silicon is very complex, and there can be variances in power delivery and frequency scaling from chip to chip.  By implementing these AVFS modules, AMD is able to monitor and adjust voltage and frequency across the entire chip to optimize overall efficiency.  These modules can tell when areas require more or less voltage, and adjust power delivery as needed.  Instead of a “one size fits all” voltage regulation implementation, AVFS allows AMD to tailor regulation according to usage as well as silicon quality.  It also adjusts for temperature, as efficiency decreases as temperature goes up in silicon.

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SOi3 is a low power state that achieves the same results as the older S3 state (standby).  The old S3 state was very slow to implement and was unpopular with users and OEMs.  It required the OS to respond and create the necessary backup files to turn off the necessary silicon.  AMD has implemented SOi3 to avoid any kind of OS interaction.  It is able to shut of large portions of the APU while still keeping memory and I/O active, thereby not require the OS to take any kind of action when going to standby.  It happens in less than a second and again provides very lower power consumption.

 

Carrizo and HSA

The promise of HSA has been talked about for years.  The idea of effectively and efficiently assigning workloads to either the CPU or the GPU, depending on their strengths, is an admirable goal.  It also has the promise of greater power efficiency by reducing the cycles necessary for completing a job.  Kaveri was originally touted as being one of the first HSA enabled parts, but AMD has backed down from that.  While Kaveri was being developed, the HSA specification was still undergoing changes.  By the time Kaveri was released, the specification had changed and they were moving towards 1.0 ratification.  Obviously AMD was not able to change up Kaveri to adjust for the new specification.

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Carrizo will be the first HSA 1.0 compliant part from AMD (and probably the world).  The one major portion of HSA that was missing in Kaveri is that of GPU Context Switching.  Carrizo of course supports that functionality.  This will hopefully start opening up more software capabilities and allow developers to embrace HSA.

 

Wrapping it Up

Carrizo will be offered from 12 watt TDP up to 35 watts.  This is not to say that Carrizo cannot scale above 35 watts, it is just that it will not be offered above that for the time being.  So far AMD’s higher TDP desktop parts will see a Kaveri refresh as well as the Vishera based AM3+ based parts throughout 2015.  In theory Carrizo could go higher, but to get it to be as energy efficient as it is without going to a smaller process node means a lot of compromises had to be made.  More power efficiency at lower frequencies typically results in lower top end frequencies combined with a higher power draw.  With Carrizo, AMD aimed squarely at power efficiency at those targeted TDPs.

The power efficiency of this part looks to be very good, especially considering that it is based on the latest 28 nm process node being offered by their unannounced fabrication partner.  My gut feeling here is that overall efficiency will come close to Intel’s Ivy Bridge processors, but will still trail Haswell and Broadwell.  The greatest strength of this APU will be the graphics performance for the power as well as the ability to handle HSA workloads.

It seems as though a lot of the power efficiency work going into Carrizo will translate well into AMD’s next generation of products.  So far AMD is aiming for 16 nm FinFET designs, but that does not preclude moving to a 14 nm FinFET process being offered by Samsung (and soon by GLOBALFOUNDRIES).  If those companies can get 14 nm FF up and running in a timely manner, then AMD will be on a much closer footing to Intel in terms of process technology.  Samsung has already started producing their latest Exynos SOC on 14 nm FF and are expecting final product to be released in early Q3 with the Galaxy S6 product.

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AMD is hoping that Carrizo will give them a much needed boost in the mobile space, which is still an area of growth for APUs.  From all indications this will be a much more competitive product to what Intel currently offers.  Add in the fact that the same motherboards that will work for Carrizo will also work for the lower powered Carrizo-L products.  Less complexity in the parts channel will help endear this product to OEMs.

Finally, the combination of using a very mature and (relatively) inexpensive 28 nm bulk process while having a 23% die shrink for more performance and better power efficiency should make for a less expensive and more desirable product for OEMs and consumers alike.  The inclusion of the southbridge onto the SOC will also make motherboards cheaper.  We will see if the actual chips have enough features, performance, and efficiency to compete well against Intel and their latest Broadwell processors that will be increasingly common when AMD finally gets Carrizo out the door in late Q2 of this year.

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