Everyone that reads SSD reviews knows that NAND Flash memory comes with advantages and disadvantages. The cost is relatively good as compared to RAM, and the data remains even with power removed (non-volatile), but there are penalties in the relatively slow programming (write) speeds. To help solve this, today Intel and Micron jointly launched a new type of memory technology.
XPoint (spoken 'cross point') is a new class of memory technology with some amazing characteristics. 10x the density (vs. DRAM), 1000x the speed, and most importantly, 1000x the endurance as compared to current NAND Flash technology.
128Gb XPoint memory dies, currently being made by Intel / Micron, are of a similar capacity to current generation NAND dies. This is impressive for a first generation part, especially since it is physically smaller than a current gen NAND die of the same capacity.
Intel stated that the method used to store the bits is vastly different from what is being used in NAND flash memory today. Intel stated that the 'whole cell' properties change as a bit is being programmed, and that the fundamental physics involved is different, and that it is writable in small amounts (NAND flash must be erased in large blocks). While they did not specifically state it, it looks to be phase change memory (*edit* at the Q&A Intel stated this is not Phase Change). The cost of this technology should end up falling somewhere between the cost of DRAM and NAND Flash.
3D XPoint memory is already being produced at the Intel / Micron Flash Technology plant at Lehi, Utah. We toured this facility a few years ago.
Intel and Micron stated that this technology is coming very soon. 2016 was stated as a launch year, and there was a wafer shown to us on stage:
You know I'm a sucker for good wafer / die photos. As soon as this session breaks I'll get a better shot!
There will be more analysis to follow on this exciting new technology, but for now I need to run to a Q&A meeting with the engineers who worked on it. Feel free to throw some questions in the comments and I'll answer what I can!
*edit* – here's a die shot:
Added note – this wafer was manufactured on a 20nm process, and consists of a 2-layer matrix. Future versions should scale with additional layers to achieve higher capacities.
SANTA CLARA, Calif. & BOISE, Idaho–(BUSINESS WIRE)–Intel Corporation and Micron Technology, Inc. today unveiled 3D XPoint™ technology, a non-volatile memory that has the potential to revolutionize any device, application or service that benefits from fast access to large sets of data. Now in production, 3D XPoint technology is a major breakthrough in memory process technology and the first new memory category since the introduction of NAND flash in 1989.
The explosion of connected devices and digital services is generating massive amounts of new data. To make this data useful, it must be stored and analyzed very quickly, creating challenges for service providers and system builders who must balance cost, power and performance trade-offs when they design memory and storage solutions. 3D XPoint technology combines the performance, density, power, non-volatility and cost advantages of all available memory technologies on the market today. The technology is up to 1,000 times faster and has up to 1,000 times greater endurance3 than NAND, and is 10 times denser than conventional memory.
“For decades, the industry has searched for ways to reduce the lag time between the processor and data to allow much faster analysis,” said Rob Crooke, senior vice president and general manager of Intel’s Non-Volatile Memory Solutions Group. “This new class of non-volatile memory achieves this goal and brings game-changing performance to memory and storage solutions.”
“One of the most significant hurdles in modern computing is the time it takes the processor to reach data on long-term storage,” said Mark Adams, president of Micron. “This new class of non-volatile memory is a revolutionary technology that allows for quick access to enormous data sets and enables entirely new applications.”
As the digital world quickly grows – from 4.4 zettabytes of digital data created in 2013 to an expected 44 zettabytes by 20204 – 3D XPoint technology can turn this immense amount of data into valuable information in nanoseconds. For example, retailers may use 3D XPoint technology to more quickly identify fraud detection patterns in financial transactions; healthcare researchers could process and analyze larger data sets in real time, accelerating complex tasks such as genetic analysis and disease tracking.
The performance benefits of 3D XPoint technology could also enhance the PC experience, allowing consumers to enjoy faster interactive social media and collaboration as well as more immersive gaming experiences. The non-volatile nature of the technology also makes it a great choice for a variety of low-latency storage applications since data is not erased when the device is powered off.
New Recipe, Architecture for Breakthrough Memory Technology
Following more than a decade of research and development, 3D XPoint technology was built from the ground up to address the need for non-volatile, high-performance, high-endurance and high-capacity storage and memory at an affordable cost. It ushers in a new class of non-volatile memory that significantly reduces latencies, allowing much more data to be stored close to the processor and accessed at speeds previously impossible for non-volatile storage.
The innovative, transistor-less cross point architecture creates a three-dimensional checkerboard where memory cells sit at the intersection of word lines and bit lines, allowing the cells to be addressed individually. As a result, data can be written and read in small sizes, leading to faster and more efficient read/write processes.
More details about 3D XPoint technology include:
- Cross Point Array Structure – Perpendicular conductors connect 128 billion densely packed memory cells. Each memory cell stores a single bit of data. This compact structure results in high performance and high-density bits.
- Stackable – In addition to the tight cross point array structure, memory cells are stacked in multiple layers. The initial technology stores 128Gb per die across two memory layers. Future generations of this technology can increase the number of memory layers, in addition to traditional lithographic pitch scaling, further improving system capacities.
- Selector – Memory cells are accessed and written or read by varying the amount of voltage sent to each selector. This eliminates the need for transistors, increasing capacity while reducing cost.
- Fast Switching Cell – With a small cell size, fast switching selector, low-latency cross point array and fast write algorithm, the cell is able to switch states faster than any existing non-volatile memory technology today.
3D XPoint technology will sample later this year with select customers, and Intel and Micron are developing individual products based on the technology.
This must have been the new
This must have been the new non volatile memory they were talking about introducing with the Skylake Xeon Purley platform and probably Knights Hill as well.
Let’s try to utilize a
Let’s try to utilize a current product comparison,
to keep our feet on the ground e.g.:
http://www.newegg.com/Product/Product.aspx?Item=N82E16820231801&Tpk=N82E16820231801
However, if you know where to look, G.Skill are making
DDR4 that clocks at 3666 MHz x 8 ~= 30,000 MB/second
(3666 x 8 = 29,328):
http://www.tomshardware.com/news/gskill-fastest-ddr4-memory-3666mhz,29085.html
Because this “bleeding edge” will eventually become
mainstream, as other DRAM vendors play catch-up,
we should be using a number like 30,000 MB/second
as a baseline for comparison purposes.
That raw bandwidth is certainly possible with a
modern Intel 4-channel integrated memory controller.
Now, how do Intel/Micron’s 3D XPoint specs compare to that baseline?
MRFS
This announcement truly blew
This announcement truly blew my friggin’ brain off.
Most of the “modern” (C w0t I did THAR?) DRAM chips have 1GB of memory per-chip on their board, which in itself essentially consists of four 256MB modules (thus 1024MB).
According to 3DXP’s info sheet, it’s able to stack NINE 1GB modules on the same chip die as the one the “modern” DRAM utilizes, thus 9GB instead of 1GB on exactly same space. 9GB. On a footprint that current 1GB of DRAM takes. I cannot friggin’ wait for first video cards and SSDs with this baby on board. Also…maybe it’s just me, but…doesn’t this essentially mean that ECC/non-ECC debacle is dead? Like, seriously. Absolutely. Completely. Totally. There is bound to be non-volatile options available for EVERYONE from this point on, and thus, as far as I can see it, ECC memory is basically killed off, paving the way for this technology, and since ECC is going to be dead, this can only mean that everyone is going to use this non-volatile solution in the near future. Because WHY NOT? 3DXP basically made ECC irrelevant. ECC is dead, in my opinion.
How does this technology mean
How does this technology mean that you no longer need ECC? Everything basically has some option for some type of ECC, from CPU cache to RAM to SSDs and HDDs.
Why wouldnt this itself be designed with ECC in mind just like HMC and HBM? ECC is becoming MORE important than ever as densities increase. All DDR4 has some intrinsic ECC(bus CRC).
Im really very confused by your statement since ECC of some type is starting to get built into everything.
ECC existed as a viable
ECC existed as a viable solution up to this point ONLY because it provided error correction factor for server solutions. With 3DXP stepping into the playground, ECC is basically obsolete, dead. Because 3DXP NEVER fails. It simply does not. 100% non-volatile. And it’s way WAAAAAY cheaper to produce AND it’s faster when it comes down to sheer performance. So, yeah, in my opinion, it looks like 3DXP actually killed ECC.
Well youre misinformed as to
Well youre misinformed as to why ECC has been important and is getting MORE important, not less.
Nothing “never fails” and there are MANY types of ECC and many types of errors caused by many different factors, from SEUs caused by alpha decay of the package itself to cosmic ray air showers, electromagnetic interference and other types of radiation, or physical failures or damage to the silicon itself.
XPoint will likely have plenty of ECC capability like SRAM, DRAM, HMC, HBM, flash, HDD, optical discs, networks of ALL types. Pretty much ANY part of a computer or network can have an ECC option, and as densities increase with DRAM XPoint or optical interconnects, whatever, it all needs MORE ECC since theres a lot more damage done by a single neutron or alpha particle.
Look into bit rot too, but thats another few paragraphs.
>Nothing “never fails”
Did
>Nothing “never fails”
Did you even read what I’ve said previously? How many times do I have to repeat it? 3DXP is 100% non-volatile. It will pertain all of it’s data at all times. This factor automatically kills ECC memory and also UPS devices. The only reason why server holders still use ECC right now is because of automatic error correcting, and LITERALLY the ONLY reason why people buy that UPS crap is because they’re afraid to lose crucial bits (pun intended) of data in the case if power suddenly goes down. Paranoiacs, both of these types of users. 3DXP completely eliminates this paranoia as a factor itself. With 3DXP you simply CAN’T screw up the data by sudden electricity outage or power bursts. All of the data will have it’s integrity at 100% correct state the next time the power returns to the device, with 3DXP. Don’t you see it?
Maybe there’s misunderstanding between us on what ECC stands for in those posts of mine. If so, then I’ll clarify it further: when I say “ECC” I solely mean the “ECC memory”, or, rather, ECC “memory kits”. Basically, when I’ve said “ECC” previously, all I’ve meant is server RAM modules which have ECC on their board. After all, this is what ECC is being used for, these days. And that is exactly what’s being killed off by 3DXP, in my opinion. That exact type of memory product. Mainstream (non-server) RAM solutions, by 99.99% of it all, do NOT have ECC on their board, if (for some reason) you don’t know. It’s funny to read how you say “any part of a computer can have ECC support”, but when memory which your computer configuration uses simply doesn’t have ECC on it’s board, it can’t use ECC, so that “any part of a computer” really makes me smile.
P.S. I know perfectly fine what a “bit rot” is, as well as what “inevitable cell discharge” is. Don’t act like you’re the definite mister know-it-all here, because it’s pretty clear to me that you’re not.
Im not acting like Mr.
Im not acting like Mr. Know-It-All at all. What youre saying is just extremely misguided.
ECC has nothing to do with losing data stored in RAM because of power failures. Similarly UPSs aren t ONLY to prevent data loss from volatile memory losing power.
ECC has to do with detecting and correcting errors from several sources: subatomic particles flipping bits is one of the main ones. Electromagnetic radiation causes significan amounts of errors even at sea level.
Even the materials that RAM is packaged in undergo subatomic decay, and release subatomic particles which flip bits in RAM. If that means a change in financial data, a single event upset(soft error) can cost millions of dollars. For an average PC user it might mean a BSOD ro game crashing, which is why most home users dont get ECC RAM.
ECC is actually used in storage media of all types, even in computers without ECC DRAM. Like i said, network protocols use it in different forms as well. You dont need ECC ram to have error correction somewhere in your PC.
And saying that XPoint memory doesnt need ECC because its nonvolatile indicates that you dont understand why ECC is used at all, or why error correction is currently used in nonvolatile flash.
Its because power loss is NOT why you use ECC or TMR with voting or DEDSEC or rad hard CPUs or FPGAs or error correction in any of its forms. SEUs are the main reason.
I’m going to weigh in here,
I’m going to weigh in here, just enough to be dangerous.
And, I much appreciate the superior comments made above
by people with much more hardware savvy than I will
ever have.
The first half of “error correction” is error detection.
Whether correction is possible depends entirely on the
mechanism chosen to do detection.
For example:
a simple parity check will tell you if a bit has
switched from 0 to 1, or from 1 to 0, but it won’t
help you identify which bit switched.
Google what is a parity check?
and find:
“A parity bit, or check bit is a bit added to the end of a string of binary code that indicates whether the number of bits in the string with the value one is even or odd.”
The objective of error “correction” is to identify
which bit or bits changed, and to reverse their value
so that the intended binary string is correct.
There are numerous ways in which “correction” can occur.
For example, with very small packets, like the
8b/10b legacy frame, that frame can simply be
re-transmitted with the correct 10 bits.
And, of course, the trailing “stop bit”
can operate as a parity bit (see above).
Here, do some homework to identify how PCIe 3.0
transmits a 128b/130b “jumbo frame” reliably
(1 start bit + 16 data bytes + 1 stop bit).
And, do the same to identify how USB 3.1
transmits a 128b/132b “jumbo frame” reliably.
What “error correction” logics are built into
PCIe 3.0 and USB 3.1?
With longer binary strings, the mechanisms
required to “correct” 1 bit errors will
necessarily become more complex, and those
same mechanisms may only “detect” 2 bit errors
but be unable to correct both errors:
if 0…1 is not correct,
is 1…1 correct?
is 1…0 correct? or
is 0…0 correct?
I suspect it is premature, and unrealistic,
to credit this new technology with 100%
perfect reliability, particularly at this
very early stage when very few of us have
any 3D XPoint memory to work with.
p.s. If my 40+ years of experience have told me
anything, it is to avoid the mistake of assuming
marketing claims equal empirical performance
one hundred percent of the time.
See the film “Fail Safe” for a crude but
relevant analogy:
http://www.imdb.com/title/tt0058083/
MRFS
There are MANY different
There are MANY different methods for correcting or detecting errors. The specific method depends on what the errors are being detected and corrected in(RAM, optical discs, networks, flash etc.).
The specific method is unimportant in the context of this discussion though.
The REASON error correction is used in the first place is the important thing. Data loss from losing power is NOT one of them as that guy seems to think.
Neutrons and other subatomic particles are the main reason ECC is necessary in RAM. They have many sources like cosmic ray air showers, solar events, terrestrial radiation sources, and even radioactive decay of the materials in the RAMs packaging itself.
Like i said, a single flipped bit could cost millions or make a satellite fail. Space based processors and RAM have even more elaborate methods for correcting errors caused by radiation.
A UPS similarly has more function than preventing data loss from the fact that DRAM is volatile. Different tiers of datacenters and computing require higher levels of reliability and uptime.
Physical damage and stopping mission critical operations in places where ECC and UPSs are used is unacceptable because of the downstream effects of even one minute of downtime.
Dont believe me? Read up on how mainframes and supercomputers(very different from each other) work, where entire CPUs, memory modules or nodes can fail and operation continues seamlessly.
Some DATACENTERS are designed with TOTAL REDUNDANCY. Two physical datacenters both running as mirror images hundreds or thousands of miles apart to prevent ANY downtime.
Yeah XPoint is non-volatile but it certainly has built in ECC capabilities and it definitely doesnt mean the end of ECC, TMR or any other error correcting method.
There are MANY different
There are MANY different methods for correcting or detecting errors. The specific method depends on what the errors are being detected and corrected in(RAM, optical discs, networks, flash etc.).
The specific method is unimportant in the context of this discussion though.
The REASON error correction is used in the first place is the important thing. Data loss from losing power is NOT one of them as that guy seems to think.
Neutrons and other subatomic particles are the main reason ECC is necessary in RAM. They have many sources like cosmic ray air showers, solar events, terrestrial radiation sources, and even radioactive decay of the materials in the RAMs packaging itself.
Like i said, a single flipped bit could cost millions or make a satellite fail. Space based processors and RAM have even more elaborate methods for correcting errors caused by radiation.
A UPS similarly has more function than preventing data loss from the fact that DRAM is volatile. Different tiers of datacenters and computing require higher levels of reliability and uptime.
Physical damage and stopping mission critical operations in places where ECC and UPSs are used is unacceptable because of the downstream effects of even one minute of downtime.
Dont believe me? Read up on how mainframes and supercomputers(very different from each other) work, where entire CPUs, memory modules or nodes can fail and operation continues seamlessly.
Some DATACENTERS are designed with TOTAL REDUNDANCY. Two physical datacenters both running as mirror images hundreds or thousands of miles apart to prevent ANY downtime.
Yeah XPoint is non-volatile but it certainly has built in ECC capabilities and it definitely doesnt mean the end of ECC, TMR or any other error correcting method.
Sorry about the double post.
Sorry about the double post. Posted from my phone. Please delete one of them.
Installing a 20GB video game
Installing a 20GB video game SOLELY on my video card, completely cornering around HDD/SSD and everything? DO WANT.
I really hope this becomes a thing by 2018 or 2022. My Reggie is finally going to be body by that time, that’s for sure.
That would be an unlikely
That would be an unlikely use. If you have a 20 GB video game, that 20 GB is probably a compressed format that must be expanded before it can be used. Keeping the compressed format in memory probably wouldn’t be tha useful. Anyway, in a few years, I doubt there will actually be any separate video cards. We will have the entire system on a single small board. You will have CPUs, GPUs, memory, and possibly a lot of other dies on the same package.
USB 4.0 by 2020.
USB 4.0 by 2020. Coincidence?
Clock rate of PCIe 4.0
Clock rate of PCIe 4.0 chipsets is planned to be 16 GHz:
https://en.wikipedia.org/wiki/PCI_Express#4.0
http://www.kitguru.net/components/graphic-cards/anton-shilov/pci-express-4-0-with-16gts-data-rates-and-new-connector-to-be-finalized-by-2017/
http://www.eetimes.com/document.asp?doc_id=1326922&page_number=1