10nm Sooner Than Expected?
It seems only yesterday that we had the first major GPU released on 16nm FF+ and now we are talking about ARM about to receive their first 10nm FF test chips! Well, in fact it was yesterday that NVIDIA formally released performance figures on the latest GeForce GTX 1080 which is based on TSMC’s 16nm FF+ process technology. Currently TSMC is going full bore on their latest process node and producing the fastest current graphics chip around. It has taken the foundry industry as a whole a lot longer to develop FinFET technology than expected, but now that they have that piece of the puzzle seemingly mastered they are moving to a new process node at an accelerated rate.
TSMC’s 10nm FF is not well understood by press and analysts yet, but we gather that it is more of a marketing term than a true drop to 10 nm features. Intel has yet to get past 14nm and does not expect 10 nm production until well into next year. TSMC is promising their version in the second half of 2016. We cannot assume that TSMC’s version will match what Intel will be doing in terms of geometries and electrical characteristics, but we do know that it is a step past TSMC’s 16nm FF products. Lithography will likely get a boost with triple patterning exposure. My guess is that the back end will also move away from the “20nm metal” stages that we see with 16nm. All in all, it should be an improved product from what we see with 16nm, but time will tell if it can match the performance and density of competing lines that bear the 10nm name from Intel, Samsung, and GLOBALFOUNDRIES.
ARM has a history of porting their architectures to new process nodes, but they are being a bit more aggressive here than we have seen in the past. It used to be that ARM would announce a new core or technology, and it would take up to two years to be introduced into the market. Now we are seeing technology announcements and actual products hitting the scenes about nine months later. With the mobile market continuing to grow we expect to see products quicker to market still.
The company designed a simplified test chip to tape out and send to TSMC for test production on the aforementioned 10nm FF process. The chip was taped out in December, 2015. The design was shipped to TSMC for mask production and wafer starts. ARM is expecting the finished wafers to arrive this month.
Test chips are typically not complex so that there is a greater chance of them working in initial production. After testing and design changes, more complex products are then sent to the new process nodes. There is no use sending a large and complex design on a new node and then having that chunk of silicon not working and having no idea why. The 10nm design starts around a core technology code named “Artemis”. It is a quad core module based on an unannounced architecture. It is attached to a single Mali GPU core (not specified, but most likely a T8x0 series GPU). These are connected by the simpler AMBA AXI interconnect. The asynchronous bridge acts as the I/O and memory subsystem. It then attached to the AHB interconnect and other system IP packages.
The expected results of this chip are fairly decent for a non-optimized design on a brand new process node. ARM expects a 12% increase in performance/speed while consuming the same power as a product produced on 16nm FFLL. When performance is equal, they expect a 30% reduction in power consumed.
In this slide we see the expected speeds of this Artemis based chip that is not optimized or truly hardened for TSMC’s 10nm FF process. The results in overall speed are very close to the production ready Cortex A-72 on TSMC’s 16nm FF+ process. What is interesting is that ARM expects Artemis POP on that same 16nm FF+ process to be a higher frequency part. These figures suggest that while in such an initial state that raw clock speed will be lower, overall power is going to be significantly lower.
Production designs from ARM using 10nm FF will most likely be high end/premium smart phones and tablets. The extra performance and power efficiency will allow for greater battery life while pushing rich content. It will also allow the continued push for smaller and thinner designs without requiring bigger batteries to achieve such performance.
I am pleasantly surprised that TSMC is offering a 10nm FF class process for production in the second half of this year. We will learn more and more about this particular process as it comes closer to fruition, but we know by these numbers that it will be a more power efficient node with some density improvements that will push it well beyond what 16nm FF+ can provide.
By implementing such a test chip on an advanced process node, ARM is getting a lot of the legwork done to improving their POP services to interested licensees. Do not expect 10nm mobile parts by the end of this year, but they should actually be arriving by mid-2017 depending on what partners end up doing. We have seen 16nm parts from TSMC and their partners over the past year, but it seems only now that 16FF+ is rolling along at a good pace. Jumping to 10nm will take TSMC some time, but all indications point to them being able to actually offer risk production this year with full production next year.
Josh, how long do you think
Josh, how long do you think it will take before we see GPU’s from AMD and/or Nvidia on this new 10nm process node?
At least a year. Have no idea
At least a year. Have no idea if this particular flavor of process is appropriate for a large GPU. It wasn't until TSMC had 16nm FF+ that NV jumped on that node.
I read somewhere, here or on
I read somewhere, here or on another site, that 10nm will be targeting mobile chips, not GPUs. Of course if 10nm is a marketing term for more advanced 14nm/16nm, that could be wrong, but is there a chance to see 20nm repeating themselves in GPUs with 10nm?
P.S. If GlobalFoundries fail to deliver with Polaris, please next time use subscript instead of capital letters.
Eventually GPUs will go onto
Eventually GPUs will go onto 10nm, but we just don't know when it will be appropriate for those types of chips. I don't think we will see the issues at 20nm pop back up at 10nm. FinFETs have more legs than that compared to planar at 20. Also, we don't know how aggressively sized TSMC's 10nm process is. My best guess is that geometries are probably close to what Intel offers now at 14nm.
What interests me more then
What interests me more then the top end is the bottom. I want my phone to idle down as low as possible since 90% of the time its sitting in my pocket waiting to do something not running a game or app.
I sorta wish companies would
I sorta wish companies would take advantage of 22nm FDSOI for that exact thing. Sure, it is a larger process… but ARM chips can be pretty small. Back bias on FDSOI makes it so idle power is super, super low.
This new 10 nm miraculous
This new 10 nm miraculous process looks more like a marketing scam than a techonological improvement…
How many gates per transistor are used? How much cost defects?
I assume this printing process couldn’t be profitable for big powerful chips.
We don’t know density or
We don't know density or other physical characteristics of 10nm so far. It is still in testing with risk production coming up later. Triple patterning does take far more steps and is more complex to perform, thereby increasing time to wafer finish and the costs involved. I don't think it is a scam, but it is certainly very early.
I think there is no surpise
I think there is no surpise this so-called 10nm process is aiming the ARM architecture rather than the x86 or AMD64 architecture. It is likely this process isn’t very reliable to be used with powerful and highly clocked chips.
The scam from my POV lies in the fact that TSMC promotes its 10nm process as if it is currently as reliable as the previous one giving wrong expectations to consumers.
So ARM holdings has a few new
So ARM holdings has a few new code names, “Ares, Prometheus, Artemis, Ananke and Mercury” but are they all still going to be of the narrower superscalar designs, or will ARM Holdings produce a beefed up reference design wider order superscalar design more similar to Apple’s A7 and A8/A9 designs.
It’s great that ARM holdings has partnered with TSMC for the 10nm test roll out of some engineering samples, as that help both ARM and its customers/IP licensees and TSMC in getting these new reference designs to market. But has ARM Holdings ceded the high end custom ARM based market to its top tier architectural licensees(Apple, AMD(K12), Samsung, Qualcomm/others). So will AMD and its K12 custom ARMv8A ISA running design make AMD a potential customer for this process, as well as Apple and its newer A series designs.
It looks like AMD’s custom K12 may be the only CPU, or APU/K12, AMD design to compete with Apple’s A series custom designs, and SMT capabilities may be the next step taken by the custom high end/high performance ARM SOC makers if they want to get a little better IPC performance out of their new designs. Until AMD gets its K12 to market the device makers without in house custom ARM designs of their own have to compete with Apple’s custom ARM designs(A series), but with AMD coming out with its K12 based APUs/CPUs that others may use it may give those device makers without any in house engineering resources of their own way via AMD’s K12 that will allow even more mobile device makers to compete with the Apple A series processors.
I’m just thinking about how much ARM cores, or extra GPU assets that AMD could get on its custom K12 cores/GPU APU designs if AMD where to go to this 10nm process while also using its high density design libraries to design some custom ARMv8A running K12 cores and get that 30% planar extra saving on top of the planar savings of going to a 10nm process node. The using of the high density design libraries to design the Carrizo cores got 30% planar space savings for AMD at 28nm, without AMD having to go to a smaller process node, so using those high density design libraries for CPU core automated layout should net those very same savings for AMD at 14nm, 10nm and smaller if going smaller than 10nm is ever going to be economically feasible.
Any AMD custom K12 ARMv8A ISA running APU will be something that no others could compete with, especially if they where running Polaris graphics, to date AMD is the only one with a/some HSA 1.0 compliant APU designs!
edit: resources of their own
edit: resources of their own way via AMD’s K12
to: resources of their own a way via AMD’s K12
This is most likely more akin
This is most likely more akin to Intel’s 14nm than real 10nm. Just like the 16FF is more akin to a 20nm node.
A 10nm FF circuit with a
A 10nm FF circuit with a higher circuit pitch(distance between circuits would still have an advantage in some areas over the 14nm process from Intel, as Intel’s 14nm circuit gate size would still be 4nm larger. So the 14nm or any nm(x) process gains most of the advantages from the actual circuit gate size and actual gate geometry and not the circuit pitch! So Intel’s 14nm process has a smaller pitch for a little denser circuit packing relative to others’ 14nm processes, and Intel’s second generation 14nm process has a little bit larger fins into the Z dimension over some of the other 14nm process, but even the FF process is running into scaling issues and Moore’s law/observation running out! (1)
most of a process node’s advantage comes from the circuit’s gate size and gate geometry, with the smaller circuit pitch only allowing for more circuit density relative to the other processes with larger pitch sizes!
(1)
“FinFET Scaling Reaches Thermal Limit”
“Advancing to the next process nodes will not produce the same performance improvements as in the past.”
http://semiengineering.com/dennards-law-and-the-finfet/
Good article
Good article