Bristol Ridge Takes on Mobile: E2 Through FX

AMD is announcing their Bristol Ridge APU family of products for mobile

It is no secret that AMD has faced an uphill battle since the release of the original Core 2 processors from Intel.  While stayed mostly competitive through the Phenom II years, they hit some major performance issues when moving to the Bulldozer architecture.  While on paper the idea of Chip Multi-Threading sounded fantastic, AMD was never able to get the per thread performance up to expectations.  While their CPUs performed well in heavily multi-threaded applications, they just were never seen in as positive of a light as the competing Intel products.

The other part of the performance equation that has hammered AMD is the lack of a new process node that would allow it to more adequately compete with Intel.  When AMD was at 32 nm PD-SOI, Intel had introduced its 22nm TriGate/FinFET.  AMD then transitioned to a 28nm HKMG planar process that was more size optimized than 32nm, but did not drastically improve upon power and transistor switching performance.

So AMD had a double whammy on their hands with an underperforming architecture and limitted to no access to advanced process nodes that would actually improve their power and speed situation.  They could not force their foundry partners to spend billions on a crash course in FinFET technology to bring that to market faster, so they had to iterate and innovate on their designs.

Bristol Ridge is the fruit of that particular labor.  It is also the end point to the architecture that was introduced with Bulldozer way back in 2011.


The 9000 Series of APUs

Bristol Ridge is now officially the 9000 series of APUs from AMD.  It is based on the very latest Excavator core and features the same GCN 1.2 version that powers the Fury cards.  It is still a 28nm HKMG based product, but there have been some tweaks involved that allows AMD to extract more performance out of the chips.

The first wave of Bristol Ridge chips are aimed at the mobile market.  This is an area where AMD has had more than a few issues truly breaking into.  Their marketshare there is lower than what we see on the desktop, but the introduction of Carrizo last year helped improve that particular situation.

The overall design of Bristol Ridge is based on Carrizo and no major architectural changes were implemented to differentiate the two chips.  This is not to say that AMD has done nothing to the chip.  What AMD has in fact done is develop a series of technologies that extracts every ounce of performance and efficiency that the architecture can provide.  So while at the macro level the two chips are near identical, when we get down to the nuts and bolts there are many changes in how power is delivered, how clocks are maintained, and how TDP is controlled.

The mobile parts are rated between 15 watts and 35 watts.  AMD is not currently announcing Bristol Ridge for the AM4 platform and higher TDPs.  We have no word on when those will hit the scene, but it certainly will not be within the next month.  AMD is focused on these low TDPs as it is an area that they have not truly broken into.  It also is not easy to design a chip that can handle TDP ranges that go from 15 watts up to 95 watts.  So AMD aimed these parts at the lower TDPs to try to gain some much needed marketshare in an area where margins are still very respectable.  My guess is that AMD will probably provide Bristol Ridge for AM4 at around a 65 watt TDP, which looks to be about the highest they can push these products without suffering some real issues with power and maintaining high clockspeeds.

The basics of Bristol Ridge is that it is comprised of two Excavator modules (4 cores), eight GCN cores (512 stream units), and an integrated south bridge.  It is a full SoC in that it has everything it needs to run a PC.  It is also AMD’s second HSA 1.0 compliant part (the first being Carrizo).  It features the 124 bit DDR3/DDR4 memory controller with speeds up to DDR4-2400.  What is perhaps a little disheartening is that it features only 12 PCI-E 3.0 lanes.  This may be perfectly fine for the mobile market, but it will likely limit the AM4 platform to 8 usable lanes off of the APU (much like the current X4 845 on the FM2+ platform).

The FX, A12, and A10 APUs are positioned for the midrange and higher end laptop market.  These will include 15 and 35 watt parts that have the most aggressive clocks and support for DDR4-2400 memory.  The A9, A6, and E2 APUs are positioned for the entry and lower midrange markets with support for up to DDR4-2133 memory and clocks focused on far surpassing those of last year’s parts in this sector.

These APUs all feature the latest UVD 6.0 unit which has VP9 and H.265/HEVC support.  AMD has focused on getting these formats to play back at the necessary resolutions and rates while sipping power.

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