Performance Comparisons – Caching and SLC / TLC Write Speed
I've chosen to split the caching results off of the respective product pages in this review so that we can better compare them side-by-side on this page. First lets look at 750 EVO vs. 850 EVO at each capacity point:
For the 120GB and 250GB capacities, the 750 and 850 EVO both carry the same 3GB SLC TurboWrite cache, but the 850's 3D VNAND has faster TLC write speeds than the planar NAND equipped 750 series products.
An oddity noted here with the 500GB model of the 750 EVO – its SLC speed fell a bit shy of the 500 MB/s of its two smaller capacities. TLC speed kicks in at 6GB written and with it we see another 100 MB/s increase over the 250GB model, which is abnormally slow (we expect TLC speeds to double with a doubling in capacity). This effect does occur with the 850 EVO of the same capacity – that model's TLC speed doubles from the ~300 MB/s of its 250GB variant, shifting the bottleneck to its SATA interface, meaning there is no distinct transition between SLC and TLC during a sequential write workload.
MX300 enjoys a good sized cache as Micron's Dynamic Write Acceleration technology can flip sections of flash between SLC and TLC modes. Since this is dynamic, it is possible to see larger or smaller runs at SLC speeds, varying by percent fill and recent write activity.
The Intel 600p, despite being a fairly quick NVMe SSD with plenty of interface bandwidth, falls a bit flat once it has exhausted 16GB worth of continuous writing. The stuttery behavior seen once its cache is full boils down to Intel's chosen caching method, which is unable to write directly to TLC once the SLC has been filled. Sure you must write 16GB or more at >100 MB/s to reach the intermittent 30 MB/s activity seen above, but it is certainly something to note for the heavier users out there.
The SanDisk Ultra II and WD Blue show only minimal write caching (likely DRAM) during this test. The Blue is supposed to have an SLC cache, and it did show higher than 300 MB/s writes in our burst testing, but at the point in the sequence with the test sequence where this metric was checked (half full following a long period of idle time), it showed negligible caching during repeated checks.