K7 Continued and Changing x86 Forever
Times were tough again for AMD with their products being overshadowed by Intel with the latest Northwood based Pentium 4s. AMD had survived pretty well when Intel had to rely on the very unpopular RDRAM DIMMS for their early Pentium 4s, but that quickly disappeared when Intel started to utilize higher speed DDR memory that had been introduced by AMD and their 760 chipset. Luckily AMD was not standing still. Engineers at AMD, including Jim Keller, were developing a new CPU architecture that would integrate northbridge features as well as add 64 bit support via AMD’s x86-64 implementation. Unlike Intel’s EPIC 64 bit architecture, it was backwards compatible with x86 32 bit computing. This technology would form the basis for 64 bit computing on x86 for the entire industry. Until AMD could get this product out, they had to milk every last drop of performance out of their aging Athlon architecture and the EV-6 bus and associated memory technologies.
Changing the x86 Landscape Forever
We now come to AMD’s shining moment. The release of the Athlon 64 in late 2003 marked the most successful and prosperous time for AMD in their entire history. The Athlon 64 3400+ was initially introduced at 2.2 GHz with the 3200+ at 2 GHz. These were clocked significantly lower than the competing Pentium 4 processor top end of the time, but they outperformed that product in nearly every way. The integrated memory controller and the Hypertransport connection to the chipset allowed a tremendous amount of data to be transferred at very low latencies as compared to what Intel could offer.
The architectural advantage was so great that even when Intel switched production to a lower process node, their designs could still not adequately compete with what AMD had to offer. The Prescott processor was a small step ahead of the previous Northwood core, but it soon gained the reputation for pulling a lot of power and being very hot. AMD’s chips were more energy efficient and cooler running even using a larger process node.
AMD initially implemented Athlon 64 on socket 754 which limited it to single channel DDR memory. Even with single channel AMD was able to match and exceed what Intel was able to offer. They later released the more competent socket 939 products which introduced non-ECC dual channel DDR performance. AMD continued to provide a superior product to Intel from top to bottom with their Athlon 64 architecture.
The company provided a further blow to Intel in the form of the first single-die x86 dual core processors with the Athlon X2 line in 2005. Intel countered with dual core products of their own, but these had to use the GTL+ bus to communicate with each other. It also lead to greater heat and power issues with the aging and increasingly unpopular Pentium 4 architecture. During this time AMD was selling every good CPU that came off the line and tried to produce as much as possible. Intel worked hard to limit AMD in a variety of ways that later were ruled to be uncompetitive in Europe and the US. It would take years for the courts to reward AMD and fine Intel, but during that time AMD suffered from lower potential revenues than they could have experience. That money could have gone into hiring and R&D. AMD did not exactly suffer at this time as they were recording record revenues and profits, but the anti-competitive behavior by Intel did limit that success with many large OEMs like Dell, Sony, and others.
AMD continued to iterate on the Athlon 64 parts from top to bottom and started designing a new revision that would require a new socket as well as support DDR-2 memory. Sadly for the company, they had awoken the sleeping giant with their outstanding parts.
That Didn’t Last Long
Intel struck back with the Core 2 Duo in mid-2006 and has not looked back since. With the release of the Athlon 64 Intel scrapped their Pentium 4 roadmap with Tejas and later projects. Instead they decided on an architecture that was originally developed in Israel as the Dothan/Banias mobile cores based on the older P6 architecture. Intel further enhanced this and created the Conroe chip that would power the Core 2 Duo. These 65 nm parts, though lacking on-die northbridge components, still was overall faster than what AMD could offer with their latest Athlon x2 series based on the Windsor core that added socket AM2 and DDR-2 support.
Intel quickly regained the performance crown with these chips and stopped the marketshare gains that AMD had enjoyed for the past several years. Intel went on to offer these much more efficient parts in quad core arrays using that same GTL+ bus to connect the cores. AMD cut prices dramatically to keep marketshare, but revenue continued to drop. AMD’s hope was that their new quad core architecture would be able to repeat what happened in 2003 with the original Athlon 64.
The Core 2 parts became popular with consumers up and down the stack while AMD was left with slower overall parts and no quad core competition on the consumer desktop. AMD continued to be a solid competitor in the server marketplace due to their Hypertransport infrastructure allowing very fast and affordable 2P and 4P setups. AMD attempted to get some of these products in enthusiasts’ hands by introducing concepts like “The Quadfather”, but they did not take off as they were hoping. Intel always had an answer that worked better and pulled less power in the consumer space.






Great article Josh – one of
Great article Josh – one of the best I’ve read on PCper in a while. One for the old gits to reminisce me thinks…
I originally got into
I originally got into computers in High School in the 80s, but it was really expensive so I couldn't afford anything. It really wasn't until 1996 that I had the funds to start exploring hardware. That is when I bought my first machine myself and in about 5 months had started to fiddle with it. Adding the 3DFX Voodoo Graphics card supercharged my interest. Was hooked ever since. Wished I had the chance to play with some of the older AMD parts pre-95.
Pretty much the same as me.
Pretty much the same as me. Amigas till the early 90’s, then onto 486 > P120 > Orchid Righteous 3D yadda yadda. I was 40 the other day which is depressing!
Love it. I was around for a
Love it. I was around for a lot of this, but it was before I started building; very cool to know that this CPU race at least used to be a very close one. Can only hope that becomes the case again.
These things seem to cycle
These things seem to cycle around. The only thing really different about this time is that while Intel hasn't been aggressively pushing the industry, it is certainly not in a weaker position architecturally as compared to the Pentium !!! and Pentium 4 days.
hey josh and guys thanks for
hey josh and guys thanks for the history lesson.
In my article I thought I was using k6 but I guess it was an Athlon.
Anyway thanks again.
Thanks for reading!
Thanks for reading!
Great write up josh
thank you
Great write up josh
thank you for this
Appreciate it!
Appreciate it!
“Going with a x86 decode with
“Going with a x86 decode with a “risc-y” core solved a lot of problems and we have essentially have had that solution ever since.”
I think using statements like this causes confusion. The micro-ops are not equivalent of RISC instructions. They are probably quite long and complicated because they embed a lot of information about the original AMD64 instruction and they may include a lot of run time data also, like register renaming stuff. In my opinion, RISC and CISC are obsolete terms. Modern processors are closer to CISC with a few RISC like features. The main thing you want is fixed instruction length encoding to allow for easier pipelining and super scalar, out-of-order execution. You also don’t want a large number of complicated addressing modes. Even with an old CISC ISA, those can mostly be worked around. They just have the compilers not use complex addressing modes and the complex, irregular length instruction encoding is converted to micro-ops that the backend can pipeline and such. I don’t consider even ARM ISA to be anywhere close to a traditional RISC ISA. It has a huge number of very specialized instructions which is the exact opposite of RISC ISAs. It is cleaner and simpler to decode than x86, but it is not RISC.
I seem to remember
I seem to remember discussions back in the day when talking about this way of decoding x86 instructions, and they would often term it "RISC-y". It certainly is not RISC, but you can see how they would be using such a term to describe it back in 1995.
Very good article covering
Very good article covering the major CPU milestones for AMD. I hope the younger readers who may not be that familiar with past AMD successes take the time to understand the advances made by AMD and the effect on keeping Intel R&D moving forward at a more rapid pace. As in any market, competition brings out the best in everything. Better products, better pricing and more rapid advances. Let’s hope AMD continues with the initial success of Ryzen.