Architectural Changes

AVX-512

Although the underlying architecture of the Skylake-X processors is the same as the mainstream consumer Skylake line, which we knew as the Core i7-6000 series, there are some important changes thanks to the Xeon heritage of these parts. First, Intel has tried to impart the value of AVX-512 on us, each and every time we discuss this platform, and its ability to drastically improve the performance of applications that are recompiled and engineered to take advantage of it. Due to timing constraints today, and with a lack of real-world software that can utilize it, we are going to hold off on the more detailed AVX-512 discussion for another day.

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Caching Hierarchy and Performance

We do know that the cache hierarchy of the Skylake-X processors has changed:

Skylake-X processors will also rebalance the cache hierarchy compared to previous generations, rebalancing to more exclusive per-core cache at the expensive of shared LLC. While Broadwell-E had 256KB of private L3 cache per core, and 2.5 MB per core of shared, Skylake-X moves to 1MB of private cache per core and 1.375MB per core of shared.

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This shift in cache division will increase the hit rate on the lowest latency memory requests, though we do expect inter-core latency to increase slightly as a result. Intel obviously has made this decision based on workload profiling so I am curious to see how it impacts our testing in the coming weeks.

After more talks with Intel and our own testing, it’s clear that the changes made to the mesh architecture (below) and cache divisions have an impact on latencies and performance in some applications. Take a look at our cache latency results below:

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I am showing the Core i9-7900X running at DDR4 speeds of 2400 MHz, 2800 MHz and 3200 MHz, and the previous 10-core part from Intel, the Core i7-6950X at DDR4-2400. What should be obvious to us is that the L3/LLC average latency for the new SKL-X processors is going to be higher (slower) than the previous generation by a considerable margin at the same memory speeds. A delta of 26%, to the advantage of the previous architecture, is worth keeping an eye on, even if the L2 access latencies remain essentially unchanged.

Mesh Architecture Interconnect

I wrote about this new revelation that is part of both the Skylake-X HEDT consumer processors and the Xeon Scalable product this week, but it’s worth including the details here as well.

One of the most significant changes to the new processor design comes in the form of a new mesh interconnect architecture that handles the communications between the on-chip logical areas.

Since the days of Nehalem-EX, Intel has utilized a ring-bus architecture for processor design. The ring bus operated in a bi-directional, sequential method that cycled through various stops. At each stop, the control logic would determine if data was to be the collected to deposited with that module. These ring bus stops are located at memory controllers, CPU cores / caches, the PCI Express interface, memory controllers, LLCs, etc. This ring bus was fairly simple and easily expandable by simply adding more stops on the ring bus itself.

However, over several generations, the ring bus has become quite large and unwieldly. Compare the ring bus from Nehalem above, to the one for last year’s Xeon E5 v5 platform.

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The spike in core counts and other modules caused a ballooning of the ring that eventually turned into multiple rings, complicating the design. As you increase the stops on the ring bus you also increase the physical latency of the messaging and data transfer, for which Intel compensated by increasing bandwidth and clock speed of this interface. The expense of that is power and efficiency.

For an on-die interconnect to remain relevant, it needs to be flexible in bandwidth scaling, reduce latency, and remain energy efficient. With 28-core Xeon processors imminent, and new IO capabilities coming along with it, the time for the ring bus in this space is over.

Starting with the HEDT and Xeon products released this year, Intel will be using a new on-chip design called a mesh that Intel promises will offer higher bandwidth, lower latency, and improved power efficiency. As the name implies, the mesh architecture is one in which each node relays messages through the network between source and destination. Though I cannot share many of the details on performance characteristics just yet, Intel did share the following diagram.

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As Intel indicates in its blog on the mesh announcements, this generic diagram “shows a representation of the mesh architecture where cores, on-chip cache banks, memory controllers, and I/O controllers are organized in rows and columns, with wires and switches connecting them at each intersection to allow for turns. By providing a more direct path than the prior ring architectures and many more pathways to eliminate bottlenecks, the mesh can operate at a lower frequency and voltage and can still deliver very high bandwidth and low latency. This results in improved performance and greater energy efficiency similar to a well-designed highway system that lets traffic flow at the optimal speed without congestion.”

The bi-directional mesh design allows a many-core design to offer lower node-to-node latency than the ring architecture could provide, and, by adjusting the width of the interface, Intel can control bandwidth (and, by relation, frequency). Intel tells us that this can offer lower average latency without increasing power. Though it wasn’t specifically mentioned in this blog, the assumption is that because nothing is free, this has a slight die size cost to implement the more granular mesh network.

Using a mesh architecture offers a couple of capabilities and also requires a few changes to the cache design. By dividing up the IO interfaces (think multiple PCI Express banks, or memory channels), Intel can provide better average access times to each core by intelligently spacing the location of those modules. Intel will also be breaking up the LLC into different segments which will share a “stop” on the network with a processor core. Rather than the previous design of the ring bus where the entirety of the LLC was accessed through a single stop, the LLC will perform as a divided system. However, Intel assures us that performance variability is not a concern:

Negligible latency differences in accessing different cache banks allows software to treat the distributed cache banks as one large unified last level cache. As a result, application developers do not have to worry about variable latency in accessing different cache banks, nor do they need to optimize or recompile code to get a significant performance boosts out of their applications.

There is a lot to dissect when it comes to this new mesh architecture for Xeon Scalable and Core i9 processors, including its overall effect on the LLC cache performance and how it might affect system memory or PCI Express performance. In theory, the integration of a mesh network-style interface could drastically improve the average latency in all cases and increase maximum memory bandwidth by giving more cores access to the memory bus sooner. But, it is also possible this increases maximum latency in some fringe cases.

Turbo Boost Max Technology 3.0

With the release of the Broadwell-E platform, Intel introduced Turbo Boost Max Technology 3.0 that allowed a single core on those CPUs to run at higher clock speeds than the others, effectively improving single-threaded performance. With Skylake-X, Intel has improved the technology to utilize the TWO best cores, rather than just one.

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This allows the 8-core and higher count processors from this launch to run at higher frequencies when only one or two cores is being utilized. In the two products that we have clock speeds for, that is a 200 MHz advantage over standard Turbo Boost technology. Intel hopes that this improvement in the technology gives them another advantage in any gaming or lightly threaded workload over the AMD Ryzen and upcoming Threadripper processors.

This feature seems to work as intended, with the single threaded workloads boosting up to 4.5 GHz in my testing and the two core workloads doing the same, just much less reliably.

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One thread

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Two threads

There may need to be some more software work (driver, OS or BIOS) done to get the two-core iteration of Turbo Boost Max Technology to more regularly hit the 4.5 GHz clock speed.

SpeedShift on HEDT

For the first time, the HEDT platform will get SpeedShift technology. This feature has been present since the launch of Skylake on the consumer notebook line, was updated with Kaby Lake, and now finds its way to the high performance platforms. The basis of the technology allows the clock rates of the CPU to get higher, and do so faster, in order to improve the responsiveness of the system for short, bursty workloads. It accomplishes this by taking over much of the control of power states from the operating system and leaves that decision making on the CPU itself.

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Zoomed

Comparing the Core i9-7900X to the Core 7-6950X (that does not have SpeedShift) and the Core i7-7700K (Kaby Lake) shows the differences in implementation. The 7900X reaches its peak clock speed in 40ms while the Broadwell-E processor from last year takes over 250ms to reach its highest clock state. That’s a significant difference and should give users better performance on application loads and other short workloads. Note the difference on the 7700K though: the consumer part and Kaby Lake design is even more aggressively targeting instantaneous clock rates.

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