Unboxing videos are perhaps second only to booth babe videos in terms of uselessness; however with Threadripper there is some information to convey. The mounting process for these new processors is very different than the ZIF of old and while we cannot provide you with any benchmarks we can show you how to install a Threadripper CPU properly. For those that learn more from their failures than their successes, which should be most of you, Kyle at [H]ard|OCP can give you some insight on just how fragile the pins on these new processors are.
"We show you how "easily" the AMD Threadripper comes out of the box, and some hilarity ensues, and then we take you through the simple steps of Threadripper installation. I would consider this a PSA as well because I destroyed the socket on my TR4 motherboard."
Here is some more Tech News from around the web:
- MD Ryzen Threadripper 1950x and 1920x @ Kitguru
- Intel's Coffee Lake CPUs won't work with 200-Series motherboards @ The Inquirer
- Why the Bitcoin Network Just Split In Half and Why It Matters @ Slashdot
- How to Write iptables Rules for IPv6 @ Linux.com
- Qualcomm, Win Semi reportedly to team up for 5G mobile infrastructure @ DigiTimes
- Grab a fork! Unravelling the Internet of Things' standards spaghetti @ The Register
- In the red corner: Malware-breeding AI. And in the blue corner: The AI trying to stop it @ The Register
- AK Racing ONYX Deluxe Gaming Chair Review @ NikKTech
The hard OCP moron was the
The hard OCP moron was the first of many. Let the flood of AMDelusionals wrecking their board’s fancy new LGA socket commence. The chine who bought newegg didn’t know what they were in for! First the miners dumping old cards, now this round of RMAss waste.
The last time I wrecked a pin
The last time I wrecked a pin was my Pentium 4, years after I upgraded… It’s not rocket science.
I would expect the Intel Xeon
I would expect the Intel Xeon with 6 channel memory and a smaller package than Threadripper to have much thinner, tightly spaced pins than previous Intel parts also. It really seems like we should be moving to serial connections for off package memory to reduce the pin count. How many pins would it take for similar bandwidth with pci-e physical layer signaling vs. current parallel dram interfaces I wonder. The latency would take a hit, but the pin count is getting a bit out of hand.
Booth babe videos are
Booth babe videos are certainly not useless