Ahead of the Supercomputing conference next week, Intel has announced a new market segment for Xeons called Cascade Lake Advanced Platform (CXL-AP). This represents a new, higher core count option in the Xeon Scalable family, which currently tops out at 28 cores.
Through the use of a multi-chip package (MCP), Intel will now be able to offer up to 48-cores, with 12 DDR4 memory channels per socket. Cascade Lake AP is being targeted at dual socket systems bringing the total core count up to 96-cores.
Intel's Ultra Path Interconnect (UPI), introduced in Skylake-EP for multi-socket communication, is used to connect both the MCP packages on a single processor together, as well as the two processors in a 2S configuration.
Given the relative amount of shade that Intel has thrown towards AMD's multi-die design with Epyc, calling it "glued-together," this move to an MCP for a high-end Xeon offering will garner some attention.
When asked about this, Intel says that the issues they previously pointed out with aren't inherently because it's a multi-die design, but rather the quality of the interconnect. By utilizing UPI for the interconnect, Intel claims their MCP design will provide performance consistency not found in other solutions. They were also quick to point out that this is not their first Xeon design utilizing multiple packages.
Intel provided some performance claims against the current 32-core Epyc 7601, of up to 3.4X greater performance in Linpack, and up to 1.3x in Stream Triad.
As usual, whether or not these claims are validated will come down to external testing when people have these new Cascade Lake AP processors in-hand, which is set to be in the first half of 2019.
More details on the entire Cascade Lake family, including Cascade Lake AP, are set to come at next week's Supercomputing conference, so stay tuned for more information as it becomes available!