If you blinked you would have missed a certain unboxing video, as it was posted before the NDA on the GTX 1660 Ti expired. However, a few sites managed to get some screengrabs before the video was taken down, so we now know a bit more about the card once thought to be mythical.
Image from PC World Bulgaria via [H]ard|OCP
Specifically, it was an MSI GeForce GTX 1660 TI Gaming X that was revealed to the world and while there were no benchmarks, there now seems to be physical proof that this card exists. It sports a single 8pin PCIe power connector, three DisplayPort 1.4 and a single HDMI 2.0b outputs and not a bit of RTX branding. Instead it contains 1,536 Turing Shaders and a 12 nm process "TU116" chip hidden under the Twin Frozr 7 cooler. The outputs tell us this particular card is not compatible with VirtualLink.
Drop by [H]ard|OCP for links as well as possible pricing and ETA.
For AMD fans, The Inquirer is reporting that 7nm Ryzen 3 desktop CPUs and Navi GPUs should be announced on 7 July at Computex. We should also see the new X570 chipset, though the rumour is that the current generation of motherboards will support the new Ryzen series with a BIOS update. Sadly, Navi is likely to only be announced as it is likely the release will be delayed until October, though like everything else in this post that is purely speculation based on a variety of sources and may not be accurate.
One thing we do know is that the new flagship Ryzen 9 3800X will have two eight core Zen 2 dies, offering a total of 16 cores and 32 threads. The base clock should be 3.9GHz with a top speed of 4.7GHZ, and a TDP of 125W.
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“One thing we do know is that
“One thing we do know is that the new flagship Ryzen 9 3800X will have two eight core Zen 2 dies, offering a total of 16 cores and 32 threads. The base clock should be 3.9GHz with a top speed of 4.7GHZ, and a TDP of 125W.”
Well one thing is for sure for Ryzen 3000(Desktop) SKUs, to a lesser degree, but they still similar though a little different, to the Threadripper 1000 series and TR 2000 series Zen/Zeppelin DIEs. The Ryzen 3000 series cores DIE/s and I/O DIE they are not all on one monolithic slab of silicon and therefore any direct through silicon thermal conduction will not transfer across the silicon from one of Ryzen 3000(desktop) Die/Chiplet and into the other Die/Chiplet, or the 14nm I/O die.
That’s one new bit of design chanege for Epyc/Rome, TR 3000, and also for the AM4/Zen-2 based Ryzen 3000(desktop only) series SKUs! The actual 14nm I/O die with the memory controllers/other IP will be on a separate thermally isolated silicon die that will not conduct thermaly in the horizontal direction, via direct silicon contact, any heat to the other dies on the MCM.
So as long as the cooling provided makes good cold plate contact with the Ryzen 3000 series Desktop CPU’s heat spreader then there is the possibility of some nice overclocks on one 8 core Die/Chiplet while the other 8 core Die/Chiplet can be running the OS and other non gaming realted software and not contributing as much heat due to the being isolated from that other DIEs on the MCM by some millemeters of air gap. Ditto for any 12 core/lower Ryzen 3000 variants with cores spread across 1, or 2, CPU Die/Chiplets and the 14nm I/O die.
For “Ryzen 9 3800X” the heat from one CPU Die/Chiplet will be somewhat thermally isolated from other DIEs on the MCM. And some Die/Core affinity masking can be employed to game on one 8, or 6, core Die/Chiplet and run any OS/Bloat on the other 8, or 6, core Die/Chiplet while the I/O die’s memory channels/PCIe-SERDES related heat will stay on that I/O Die’s silicon and away from the cores involved with gaming etc. For all thoes DIEs the heat will transfer to the heat spreader and hopefully into the cold plate of the cooling device and stay somewhat isolated from the others on the MCM.
Now if the rumors could just verify if there is any L4 cache on Ryzen 3000’s 14nm I/O die to help keep even more memory access latency in check.
Is the Infiity Fabric’s clock domain going to be isolated from the Memory Controller’s Clock Domain and the Infinity Fabric allowed to operate at a higher clock rate for faster data transfer and maybe lower latency also for any Chip to Chip communication on the MCM. For sure the Zen-2 core Die/Chiplets should be able to have their own clock domains and the I/O die has sufficient size to host the extra cross clcok domain circuitry required.
The I/O, PCIe 4.0, and Infinity Fabrc 2 on Zen-2 based designs:
“◾ I/O
. ◾ PCIe 4.0 (from 3.0)
. ◾ Infinity Fabric 2
… ◾ 2.3x transfer rate per link (25 GT/s, up from ~10.6 GT/s) (1)
[“.” added to maintain outline formatting lost to cut and paste HTML into Text Box]
(1)
“Zen 2 – Microarchitectures – AMD”
https://en.wikichip.org/wiki/amd/microarchitectures/zen_2