Intel’s Data-Centric Innovation Day 2019 Overview: 56-Core CPUs, 100GbE, and Optane DIMMs, Oh My
Intel’s biggest launch ever covers everything from the cloud to the edge
Intel today made a number of product and strategy announcements that are all coordinated to continue the company’s ongoing “data-centric transformation.” Building off of recent events such as last August’s Data-Centric Innovation Summit but with roots spanning back years, today’s announcements further solidify Intel’s new strategy: a shift from the “PC-centric” model that for decades drove hundreds of billions of dollars in revenue but is now on the decline, to the rapidly growing and ever changing “data-centric” world of cloud computing, machine learning, artificial intelligence, automated vehicles, Internet-connected devices, and the seemingly unending growth of data that all of these areas generate.
Rather than abandon its PC roots in this transition, Intel’s plan is to leverage its existing technologies and market share advantages in order to attack the data-centric needs of its customers from all angles. Intel sees a huge market opportunity when considering the range of requirements “from edge to cloud and back:” that is, addressing the needs of everything from IoT devices, to wireless and cellular networking, to networked storage, to powerful data center and cloud servers, and all of the processing, analysis, and security that goes with it.
Intel’s goal, at least as I interpret it, is to be a ‘one stop shop’ for businesses and organizations of all sizes who are transitioning alongside Intel to data-centric business models and workloads. Sure, Intel will be happy to continue selling you Xeon-based servers and workstations, but they can also address your networking needs with new 100Gbps Ethernet solutions, speed up your storage-speed-limited workloads with Optane SSDs, increase performance and reduce costs for memory-dependent workloads by supplementing DRAM with Optane, and address specialized workloads with highly optimized Xeon SKUs and FPGAs. In short, Intel isn’t the company that makes your processor or server, it’s now (or rather wants to be) the platform that can handle your needs from end-to-end. Or, as the company’s recent slogan states: “move faster, store more, process everything.”
Intel’s announcements cover both hardware and software/firmware. We’ll touch on the latter but focus primarily on the former before turning our attention to why Intel is making these moves. There is a lot going on with this product launch, so we’ll try to hit the key points and provide supplemental coverage as additional information becomes available.
That said, let’s jump into some of the product announcements.
2nd-Generation Xeon Scalable Processors
Intel did all the hard work back in 2017 with the rebranding and repositioning of its Xeon processors under the “Scalable” brand, leaving little opportunity for any transformative changes in this second generation. The new parts are based on Cascade Lake, which remains a 14nm microarchitecture. Cascade Lake includes hardware mitigations for Spectre and Meltdown, and some new features which we will address shortly, but considering just traditional computing power, it’s not a significant leap, in general, over Skylake. Indeed, while briefing the press on the new lineup, Intel focused on the performance benefits for enterprises on a four-to-seven-year upgrade cycle.
However, in keeping with Intel’s coordinated data-centric strategy, there are some changes that will be key for certain workloads. First, at the top end, there’s a new Platinum 9200-series lineup offering up to 56 cores/112 threads at base and turbo clocks of 2.6GHz and 3.8GHz, respectively. Oh, it also has a TDP of 400W. Pricing, surprisingly, was not disclosed.
The announcement of the 56-core SKU was a bit of a surprise considering Intel stated last fall that Cascade Lake would top out at 48 cores. But, regardless, you won’t be buying a Xeon Platinum 9282 directly, at least not officially. Intel has worked with its industry partners to design a new server chassis specifically for the highest end Cascade Lake Xeons, complete with custom compute modules featuring optional liquid cooling.
Customers with the need and budget for these sure-to-be-shockingly-expensive configurations will buy complete servers from the usual enterprise vendors.
Looking at other changes to the 2nd-Generation Xeon Scalable lineup, Intel’s Speed Select Technology on select SKUs will let users optimize their processors for specific workloads (e.g., focus on fewer cores at higher frequency, or more cores at lower frequency), ensuring that certain workloads or power requirements are prioritized as intended, and DL Boost improvements promise big gains for certain AI workloads — up to 30X, Intel claims — although even then not to the point of being price competitive with GPU solutions. Intel’s counter to the price—performance argument for AI processing was that if you already have a Xeon Scalable processor, you don’t necessarily need to go out and purchase some NVIDIA Telsas if you only have small or infrequent AI-based workloads.
This new second-generation of Xeon Scalable Processors also offers support for Optane DC Persistent Memory, which we’ll discuss further below.
With two generations of Xeon Scalable processors now on the market and numerous subdivisions within them, it’s getting a bit complicated keeping track of the naming conventions. Fortunately, Intel offers this handy guide for identifying parts based on generation, performance tier, and capabilities.
Check out the full list of new Xeon Scalable Processors:
Finally, as mentioned earlier, Intel has also introduced a number Xeon SKUs that are “optimized” for specific industries or workloads based on factors such as core count versus frequency, amount of cache or memory support, and operating conditions. Examples include value-oriented VM density, networking, and single-core performance.
Xeon D-1600 Series
Intel’s D-series Xeons are intended for situations which require a good amount of power in a compact, energy efficient configuration. Examples range from low-end servers to higher-end NAS devices. An upgrade over the D-1500, the new D-1600 lineup offers a 1.2 to 1.5X increase in base frequency with configurations between 2 and 8 cores and TDPs between 27 and 65W.
The processors also support hardware virtualization, Intel QuickAssist, up to 128GB of DDR4 memory, and up to four 10Gbps Ethernet ports.
Optane DC Persistent Memory
Intel has been talking about Optane DC Persistent Memory for quite some time now. The company’s pitch is that while Optane/3D XPoint is a great option for “traditional” solid state storage, its true potential was always limited by the interface, even fast PCIe interfaces. Optane DC Persistent Memory solves this limitation by switching to a DIMM form factor, which gives it a huge improvement in latency and “bridges the gap” between current PCIe-based flash storage and DRAM.
The point here is that DRAM is expensive, and capacities may be limited. So why not use Optane to supplement your servers’ DRAM? Intel acknowledges that Optane DC is certainly slower than DRAM, but for many workloads the amount of memory is more important to overall performance than the absolute speed (at least, up to a limit). Certain workloads may also have other bottlenecks such that any difference in speed between data stored in DRAM and Optane DC won’t be noticed (or the cost savings may be deemed to be worth the performance hit).
One interesting facet of this is that, unlike DRAM, Optane is not volatile. To prevent compatibility issues, Intel gives users the choice of running their Optane DC Persistent Memory in either Memory or App Direct modes.
In Memory Mode, the system effectively emulates traditional DRAM. It caches as much as it can to the actual DRAM and then clears the Optane DC modules every power cycle to mimic volatility. The benefit is that no software changes are required to use this mode; from the software’s perspective, it’s all just DRAM. The downside is latency will vary and be limited entirely by Optane DC when there’s a cache miss in DRAM.
In App Direct Mode, your software must be updated to take advantage of “Persistent Memory Aware” storage. That allows the system to effectively “put Optane DC in its place” by creating a new tier between DRAM and your traditional storage. Your apps know that this storage tier is non-volatile and slower than DRAM, so it will keep data stored in the optimal locations between DRAM and Optane without wasted performance on management like paging.
Again, this won’t be suitable for every workload. But if your workloads can accommodate Optane DC Persistent Memory, the costs savings can easily rise into the tens of thousands per system. You spend less on expensive DRAM, add in some slightly less expensive Optane DC modules, and you either have the same amount of effective memory for less, or more effective memory for the same cost.
In addition to Optane DIMMs, Intel detailed two new Optane SSD options. The first is a dual port version of the enterprise-grade Optane DC SSD, allowing for both improved performance and resiliency for critical applications.
More unusual was the Intel SSD D5-P4326, a long ruler-shaped SSD using the E1.L form factor. Using QLC flash, it’s a cost-optimized option and its unique form factor means you can squeeze lots of them (up to 1PB) in a 1U chassis.
The reason for Intel’s embrace of QLC flash for the enterprise mirrors that of companies producing QLC drives for the consumer and small business market: mass market adoption. QLC-based SSDs lag their MLC and TLC competitors in terms of both burst and sustained performance, but in most cases they still easily beat traditional spinning media. Making flash cheaper and denser allows enterprises to move more and more data to “warm” storage: not as fast as your high-end Optane or 96-layer TLC drive, but much more accessible than mechanical drives when you need it.
Intel Ethernet 800 Series
With all the processing and local data management, Intel didn’t forget about actually moving data between locations. The company announced its latest Ethernet chipset, the Ethernet 800 series. Codenamed “Columbiaville,” it supports speeds of up to 100Gbps.
Beyond the base bandwidth increase, Intel is using Application Device Queues (ADQ), a feature that can queue and steer application-specific packets for better performance consistency, reduced latency, and in some cases greater throughput.
It’s doing more than the familiar network QoS; ADQ can link supported applications directly to specific queues, which can reduce latency in addition to maintaining throughput.
The final product to touch on is the Agilex FPGA, a chiplet-packet 10nm-based part utilizing 3D system-in-package (SiP) technology that can be highly customized for specific workloads or interoperability. Options include DDR5 and HBM memory, Optane DC Persistent Memory, multi-gig networking, PCIe 5.0, and cache coherency with Xeon Scalable processors.
The Agilex series will be available in three variants targeting different performance levels and capabilities.
We’re still waiting on complete pricing information as of the date of publication, but Intel is at least officially announcing availability for most of the new products.
- 2nd-Generation Intel Xeon Scalable Processors (with the exception of the Platinum 9200 Series)
- Xeon D-1600
- Optane DC Persistent Memory
- D5-P4326 SSD
Available Q3 2019:
- Intel Ethernet 800 Series (mass production; samples shipping now)
Available H2 2019:
- Agilex FPGAs
- Xeon Platinum 9200 Series (some systems to ship H1 with ramp up for H2)
- Optane DC SSD D4800X
What’s Driving Intel’s Transformation?
Now that we’ve sampled what Intel launched, the next step is to ask the same question we’ve asked at each juncture in Intel’s now multi-year transformation: why?
There are a multitude of factors at play when attempting to analyze the reasons for Intel’s shift. But three factors stand out: the declining PC market, the new and urgent needs of the “data-centric” technology sector, and, perhaps most importantly, the arguably surprising emergence of a legitimate competitor in the enterprise.
The first factor is clear and obvious. The stall and later decline of a market so long dominated by a single company is, of course, bad news for that company. So, regardless of any other justification, Intel’s push to expand its total addressable market is necessary to counter an existential threat.
The second factor is the one that Intel officially acknowledges and promotes: the data problem. From traditional data such as enterprise databases to the constant logging and transfer of information via telecommunication networks, cloud computing, artificial intelligence and analytics, and IoT devices, the global technology industry is creating a surge in data generation that Intel argues can’t be accommodated by current processing, storage, and networking infrastructures.
For example, a report late last year from Seagate and IDC claimed that about 33 zettabytes (33 billion terabytes) of data was created in 2018. That number is expected to grow to 175 zettabytes per year by 2025. The view of Intel and other companies looking at this issue is that existing solutions simply can’t move, store, and process this much data. Intel stated in its press release for this event that only about “two percent of the world’s data has been analyzed.”
The argument is that this growing gap between the amount of data generated and the amount we can process with existing hardware and software deprives companies and consumers of any benefits that data may provide. Therefore, by offering a coordinated suite of products and services supposedly designed for this very challenge, Intel can help its customers begin to regain control of the situation and start to make up ground.
The final and most interesting factor, particularly for many in our audience, is AMD and the remarkable progress the company has made over the past two years thanks to the Zen architecture. With Ryzen on the desktop and EPYC in the data center, for the first time in years AMD is putting up a legitimate challenge to Intel at almost all performance tiers, especially when considering the price–performance ratio.
The somewhat good news for Intel is that AMD’s market share gains have failed to keep pace with its performance gains…at least thus far. AMD saw an increase in market share last year for all traditional categories (server, desktop, laptop), but while the company’s server share more than doubled, it’s still sitting in the low single digits.
Now AMD is readying the next generation of EPYC parts, codenamed “Rome.” AMD’s teaser late last year and a string of leaks since then all point to the likelihood that, in certain workloads, Rome will outperform its Xeon Scalable counterparts at notably lower cost and include additional features such as PCIe 4.0. These relative surges in performance for AMD are hitting just as Intel is hoping to overcome the years of process technology challenges that stalled the company’s CPU development at 14nm.
Intel won’t lose every performance tier to AMD, of course. Certain workloads still perform better with Intel’s architecture and, in an interesting role reversal from the Opteron days, EPYC servers are limited to two sockets while Xeon Golds can go up to four sockets and Xeon Platinums up to eight. But Intel faces the very real threat of losing head-to-head comparisons in terms of pure performance, let alone price or availability. Why not then, simply, change the game?
Intel still commands an overwhelming share of the sever market, in excess of 96 percent. This is an incredibly lucrative market, and Intel isn’t wrong about the challenges this market faces involving the data growth and management problem. The mission for Intel, as those initial Rome benchmarks and pricing figures start to show up, is to convince its current (and potential) customers that losing by a few percentage points over here is easily offset by, for example, the cost savings of Optane DC Persistent Memory over there. Intel’s acquisition and development of storage, networking, and, increasingly, graphics, gives the company a broad menu of solutions that it can present to customers tempted to jump to EPYC. At least, again, in theory.
As this article is posted, I’m in San Francisco attending Intel’s official launch. The company briefed us last month on the technical and strategic side of things, but one thing missing was the customer’s perspective.
Intel’s strategy relies significantly on how well it has read both the needs of its customers as well as the degree to which those customers value price and performance in each product category. I’ve already heard Intel’s side; my goal this week is to hear from customers — albeit customers carefully selected by Intel — about more real-world examples of what happens when Intel’s planning is put into practice.
The remainder of 2019 should be a bit wild in terms of server market share and perception, as AMD fires its next salvo while Intel continues to promote its new vision. The slow, calculated nature of enterprise-level hardware upgrades means that Intel’s market share dominance won’t end soon, but If both companies can secure sufficient vendor partners (AMD was especially hampered last year by having limited availability of EPYC for months) and consistently meet demand, we could see a major escalation in this new server war.
What’s the cache coherent cpu
What’s the cache coherent cpu interface on the FPGA? UPI?
Will this FPGA just fit into a XEON socket?
UPI currently, yes. And looks
UPI currently, yes. And looks like it will be available in card form initially. Check out the coverage at STH for more details.
“with the exception of the
“with the exception of the Platinum 9200 Series”
So the high core count SKUs are a good while off from RTM and so Epyc/Rome will be here before Intel can compete. Even the Epyc/Naples SKUs have more Memory channels per socket at 8 memory channels per socket and that’s including 128 PCIe 3.0 lanes on 1P and 2P Epyc/Naples SP3/MB platform offerings. Epyc/Rome will go to 128 PCIe 4.0 lanes and make use of 64 Infinity Fabric 2.0 lanes between the sockets at much higher bandwidth for IF-Ver2.
Wikichip’s Zen-2 entry states that Infinity Fabric 2 will offer 2.3x transfer rate per link (25 GT/s, up from ~10.6 GT/s).
“The somewhat good news for Intel is that AMD’s market share gains have failed to keep pace with its performance gains…at least thus far. AMD saw an increase in market share last year for all traditional categories (server, desktop, laptop), but while the company’s server share more than doubled, it’s still sitting in the low single digits.”
Really AMD’s only in the 1P and 2P server market and Lisa Sue did state that in the quarterly confrence call that AMD’s Mid Single Digit market share numbers where met and that AMD expects low double digits by the end of 2019 into the first Quarter of 2020. The entire AMD earnings confrence transcript is avialable and AMD did make that clear. It’s easy for sorces to spin that mid dingle digit AMD server market share numbers good or bad depending on the inclusion of the Above the 2P server market(4P) TAM/Market figures but AMD does not even compete for any 4P/4-Socket server business like Intel and IBM.
AMD’s doubling of server orders from 3Q/2018 through 4Q/2018 should be what is more noticable and the NextPlatform Quotes Lis Su as stating:
” “Fourth quarter server unit shipments more than doubled sequentially based on growing demand for our highest end, 32-core Epyc processors with cloud, HPC, and virtualized enterprise customers,” Su explained on the call yesterday after the market close with Wall Street analysts. “As a result, we believe we achieved our goal of mid-single-digit server unit share exiting 2018. We had another strong quarter of cloud adoption, highlighted by industry leader Amazon announcing new versions of their most popular EC2 computing instances powered by Epyc processors. Businesses can easily migrate their AWS instances to AMD and save 10 percent or more based on the technology advantages of our platform. Microsoft Azure also announced general availability of their AMD based storage instance in the quarter, as well as a new HPC instance powered by Epyc processors that is 33 percent faster than competitive X86 offerings.” ” (1)
So AMD’s 3rd to 4th quarter Doubling of AMD’s server market numbers could get large fast if that doubling continues. AMD’s alreading getting Epyc/Rome designs wins also as stated in the NextPlatform article.
One must watch out for any those market share figures and AMD’s server market share as some market analysis firms are including the 4P server market’s TAM/Market share figures when AMD only offers 1P and 2P, 1-Socket/2-Socket, offerings. AMD’s around 5% server market share figure is based on AMD’s 1P/2P market numbers without the 4P TAM/Marker figures included.
“AMD Nails Its Epyc Server Targets For 2018”
Benchmark summary https://openbenchmarking.org/embed.php?i=1903292-HV-SERVERCPU30&sha=432aff7&p=2 New Cascades are doing much better than Epyc.
At over twice the cost one
At over twice the cost one would certainly hope they do better.
Yeah, expensive indeed
Yeah, expensive indeed although the premium prices likely accounts for that Optane DIMM support and AVX 512 performance.
The Next Platform is listing
The Next Platform is listing the 1K unit Trey pricing on Cascade lake(1) and the 9282 Platinum’s(400 Watts TDP at 2, 28 core chips per MCM, 56 cores/112 threads) price of $20530.00. The 9282 Platinum’s 28 cores per die/2 dies per MCM well that’s not going to be as great of a high yielding Die/Wafer combination compared to AMD’s 8 core Zen/Zeppelin on Epyc/Naples or Zen-2 Epyc/Rome Die/Chiplets that do not include any Memory Controller IP(That’s on the I/O Die).
AMD will have better Die/Wafer yields on those 7nm Zen2 Epyc/Rome Die/Chiplets than even on Epyc/Naples with Zen/Zeppelin. That’s going to be what allows AMD to really get the most 7nm Zen-2 based Die/Chiplet production yields at the lowest per die cost and give AMD the better pricing latitude per MCM.
The cooling on the 9282/400-Watts-TDP is really going to need water and chilling in that density. So no wonder Intel is limiting that to 4P configurations tops. AMD’s real Price/Performance latitude looks to be still ahead of Intel until Intel can get some smaller 8 core Die/Chiplet IP that can scale across multiple lower core count CPU dies per MCM.
I’ll bet that Epyc/Rome’s 64 core SKUs are going to generate a fair amount of heat per mm^2 of CPU die being on a denser 7nm node. But TSMC’s 7nm process has got to be of help there with power savings and less leakage even with Epyc/Rome’s 256 bit FP units that are double what Epyc/Naples offered at 128 bits. AMD’s smaller Rome die/chiplets are still going to have some air gaps between the dies/chiplets so no similar amounts of lateral heat soaking via silicon heat transfer compared to 2 large 28 core dies/MCM on Intel’s highest core count offerings.
Optane SSDs can be used with AMD’s CPUs but not any Optane DIMM IP unless Micron get’s its QuantX/XPoint Products shipping within the next 6 to 8 months(not likely).
I think that Intel is Targeting IBM/OpenPower’s Power9’s more than even AMD’s Epyc(1P and 2P offerings only) as Intel is offering 4P and 8P options that AMD does not. So IBM/OpenPower paired with Nvidia Volta based accelerators moreso than just AMD/Epyc. Power9’s SMT4 and SMT8 options and plenty of threads per core for some workloads that like more processor threads.
“Intel Pushes Xeon SP To The Next Level With Cascade Lake”
Optane DIMM advantages
Optane DIMM advantages https://www.servethehome.com/wp-content/uploads/2019/04/KVM-Virtualization-STH-STFB-Benchmark-Workload-2-with-4P-DCPMM.jpg Half the DDR4 memory yet much faster when combined.
This article(1) makes an
This article(1) makes an interesting comment on the Falling DIMM prices and Intel’s memory division losing money on Optane sales and maybe Micron was wise to delay its QuantX/XPoint offerings. Micron is probably waiting for XPoint Gen-2 and better results with better controller IP before going all in with XPpint. And RAM/DRAM pricing as well as NAND Pricing is falling making it harder on Intel to amortise it’s R&D investment in XPoint memory.
Look at that data retention on Optane when not being accessed and DDR-T is a proprietary protocol as well as other things to consider:
“To attract users, Intel hopes that Optane DIMMs sell at about half the price of DRAM versions, he said. But with the current costs of ramping Optane, Intel is the only memory-chip vendor currently making a loss, he added.
“The Optane DIMMs were supposed to come out in 2017 with Skylake-SP processors but were delayed,” said Linley Gwennap of the Linley Group. “Now, the maximum capacity of DRAM DIMMs have gone up and their prices are coming down significantly — the problem is that DRAM is always getting better.” “(1)
“Intel provided some interesting insights into its designs. Like solid-state drives, Optane DIMMs sport their own controller with SRAM as well as a power management IC, capacitors, and DRAM for an address lookup table.
Up to six Optane modules can be used with a single CPU, which also needs some vanilla DRAM to boot. The Optane modules need to be nearer to the CPU for signal-integrity issues.
The boards can pack up to 11 Optane media chips, some used for error correction and redundancy. They keep security keys in both volatile and non-volatile memory stores.
Intel said that the media chips will last five years of read/write cycles. However, the data is only retained about three months when not in use. ” (1)
“Optane No Big Boost for DRAM
New Intel DIMMs show rough road ahead for new memories”
Real world tests
Real world tests https://arxiv.org/abs/1903.05714 tell a better story then pure speculations.
“Scalable nonvolatile memory DIMMs will finally be commercially available with the release of the Intel Optane DC Persistent Memory Module (or just “Optane DC PMM”). This new nonvolatile DIMM supports byte-granularity accesses with access times on the order of DRAM, while also providing data storage that survives power outages. This work comprises the first in-depth, scholarly, performance review of Intel’s Optane DC PMM, exploring its capabilities as a main memory device, and as persistent, byte-addressable memory exposed to user-space applications. This report details the technologies performance under a number of modes and scenarios, and across a wide variety of macro-scale benchmarks. Optane DC PMMs can be used as large memory devices with a DRAM cache to hide their lower bandwidth and higher latency. When used in this Memory (or cached) mode, Optane DC memory has little impact on applications with small memory footprints. Applications with larger memory footprints may experience some slow-down relative to DRAM, but are now able to keep much more data in memory. When used under a file system, Optane DC PMMs can result in significant performance gains, especially when the file system is optimized to use the load/store interface of the Optane DC PMM and the application uses many small, persistent writes. For instance, using the NOVA-relaxed NVMM file system, we can improve the performance of Kyoto Cabinet by almost 2x. Optane DC PMMs can also enable user-space persistence where the application explicitly controls its writes into persistent Optane DC media. In our experiments, modified applications that used user-space Optane DC persistence generally outperformed their file system counterparts. For instance, the persistent version of RocksDB performed almost 2x faster than the equivalent program utilizing an NVMM-aware file system. “
First benchmarks https://www.phoronix.com/scan.php?page=article&item=intel-cascadelake-linux&num=1 Looking much stronger than previous generation.
It better have stronger
It better have stronger performance for Intel otherwise the Price/Performance metrics will not be so kind to Intel.
AMD has less to worry about with Epyc/Rome with the Core counts and PCIe lane counts ahead of Intel. So Depending on the server workloads AMD will be at some sdvantage for workloads the need all the cores/threads that they can get.
AMD’s server market share percentage figures went as high as around 23% of the total server market TAM on AMD’s Opteron SKUs and we all know that Epyc/Naples, and soon Epyc/Rome, have much better overall performance figures compared to Opteron. Epyc/Naples and Epyc/Rome all come with 8 memory channels per socket and 128 PCIe 3.0, 4.0 On Rome, lanes also as standard for EPYC/SP3 MB platform. So do not forget that most of the Intel offerings only go as high as 6 memory channels per socket with only the Platinum 9200 offerings going higher than 8 memory channels per socket.
Remember that ARM(Thunder X2/Others) and IBM/OpenPower(Power9s paired with Nvidia Volta GPU accelerator SKUs) are also in the server market competition from the low and high end respectively. So it’s not only about x86 competition for some Server/HPC workloads!
Intel has more competition than just AMD.
Didn’t you check the review?
Didn’t you check the review? Power9 was also in there and got trounced. About ARM, not much news except for the recent Amazon one. Still languishing behind x86 by a very wide margin when it comes to market presence. Where does that 23% comes from? All the news says AMD’s current datacenter market share precentage still at single digits.
Another set of Cascade benchmarks https://www.servethehome.com/2nd-gen-intel-xeon-scalable-launch-cascade-lake-details-and-analysis/ strong performance across the board.
You are not very
You are not very knowledgeable, Brolly, because if I can mention Opteron and you can not place that it refered to AMD’s past server market share history then you need to go back to school.
So you can not even take the slightest time to even research Opteron and here you are trying to discuss the current AMD compared to Intel and others server market potential. And AMD with its Zen based Epyc/Naples or Zen-2 Based Epyc/Rome server market competition is going to best AMD’s Opteron numbers by a good margin in the Price/Performance metrics and server market share potential.
Stick with ESPN, Brolly, as the server market is definitely not your forte. Opteron got AMD up to around 23% server market share and Opteron was no where near as performant as AMD’s current Zen Based Epyc/Naples or the Zen-2 Based Epyc/Rome offerings. The server market is not about some top performer only it’s about Price/Performance and workload and TCO so that’s what the potential server clients will look at for their specific workloads.
Opteron’s Price/Performance metrcs sold server SKUs for AMD and that’s even more important with Epyc/Naples and Epyc/Rome where the feature sets that come standard on the Epyc/SP3 MB platform will present a greater challenge to Intel in the x86 based server market.
Those Platinum 9200 series SKUs are not even ready and will only be custom affairs and not as easy or as flexable to work with compared to socketed server solutions. Intel’s 8000/below SKUs still only offer 6 memory channels per socket and less PCIe 3.0 lanes than AMD’s Epyc/SP3 MB platfroms with their 8 memory channels per socket and 128 PCIe 3.0 lanes(Epyc/Naples) or 128 PCIe 4.0 lanes(Epyc/Rome).
Trounced is not a metric that any server client is looking at as that’s not a Price/Performance metric. There are server workloads where Power9 perform better and others where x86 performs better but any potential server customers are looking at Price/Performance and TCO to go along with their specific workload needs! Some Clients needs will be met by ARM(SMT4 on ThunderX2) based server solutions some by Power9’s SMT4 or SMT8 and some by the x86 based offerings SMT2 if the Price/Performance and TCO numbers say that’s what’s best for the client.
And IF you have to ask what TCO is then you are too far behind and would you not be better off on some ESPN forum where Trounced has more meaning.
The NextPlatform has a new article out concerning Intel’s 9200 series SKUs so go there and do some reading. Intel’s problem is not based around performance it’s based around Price/Performance and MB platfotm feature sets that come at extra costs and not standard like AMD’s Zen/Zen-2 Epyc/SP3 MB platform provides standard at no extra charge.
Strong performance across the board at what Price for what performance and MB feature sets as well as what TCO for the potential server client is what will be sussed out by the potential server clients themselves, or those server clients hired consultants. The actuaries and the consulting engineers will be looking at Price/Performance and TCO and not any Trounced metrics for raw performance alone!
Price and TCO make for sales with performance being dependent on Price and TCO. If Intel is too Pricy then that Performance may not matter and Pricy affects overall TCO because financing the pricy kit comes from the local industral bankers. So plenty of actuaries and amortization figures to look at as those server clients are actually businesses.
Brolly thinks Server CPUs are a drag race but I say that Brolly’s analysis is a drag as Brolly is not up to speed on the server market and it shows.
Then I guess you missed this
Then I guess you missed this https://www.cnbc.com/2018/04/25/amd-earnings-q1-2018.html with the paragraph..
“With its Epyc server chips, AMD has been trying to gain share in a market dominated by Intel. The chipmaker continues to expect to have mid-single-digit server chip unit share by the end of the year, Su said.”
This comes straight from the lioness mouth. Just goes to show who is really not up to speed in terms of datacenter market share information. Nowadays Power9 depended on big supercomputer and mainframe contracts to stay relevant since they pretty much lost the datacenter markets.
That’s a one year old
That’s a one year old article, chipman’s sockpuppet, so go to the other PCPer article where the same link was posted by chipman(The one with his hand up Brolly’s nether region)!
Really Chipman, it’s not very hard to suss out your aliases and your agenda. “Nowadays Power9 depended on big supercomputer” Really, chipman, your bad diction is your fingerprint that makes your sockpuppets usage worthless!
Look again, that is for Q4
Look again, that is for Q4 2018 which is only 1Q ago which not even one year old. That single digits is also verified by other sources like IDC and Digitimes. Also look how long it took Epyc from (soft) launch until the first real world deployment. Do you know that besides Epyc there are still Opterons in AMD’s current lineup?
Example of Power9’s embarassing performance https://www.phoronix.com/scan.php?page=article&item=power9-x86-servers&num=1 and also https://www.phoronix.com/scan.php?page=article&item=power9-epyc-xeon&num=1 Outisde of a very few select server vendors, only the lonely Raptor Computing sells Power related hardware for development or workstations. That is how bad Power9 situation is.
Bonus https://browser.geekbench.com/v4/cpu/12154826 you can now compare Power9’s embarassing results with other processors.
Errata, supposed to be “Q1
Errata, supposed to be “Q1 2018 to Q4 2018” which the entire year 2018. And end of 2018 is just 1Q ago.
Example https://www.tomshardware.com/news/amd-market-share-desktop-server-notebook,38561.html says “However, Mercury Research’s server share projections are lower at 3.2% unit share”
AMD’s admission “We used IDC’s server forecast of the 1P and 2P server TAM of roughly 5M units to compute our server market share estimates. We believe that in Q4 2018 we achieved ~5% unit share of the 1P and 2P server market addressed by our EPYC processors (as defined by IDC). “
That 3.2 TAM includes 4P and
That 3.2 TAM includes 4P and 8P server sales where AMD has no product offerings currently so the IDC figures are all well and proper with the SEC and AMD stating how they came to those around 5%(1P/2P) server market figures. Nothing wrong with AMD excluding any TAM server market numbers where AMD does not even have any competing 4P/8P offerings.
IF AMD did anything wrong the SEC would be all over that but it’s all proper for AMD to only use TAM/Market percentages only for markets where AMD actually competes.
Why not ask the SEC BrollyChipmanFUDsterTheThird!
Always still the same
Always still the same conclusion, AMD’s market share in single digits. Epyc forgo 4 and 8 sockets per server rack which accounts for a tiny fraction, usually for specialized applications like Oracle. The bulk majority of datacenter market share are 1 or 2 socket servers. AMD still single digit precentage in this respect.
BONUS HA! Geekbench is a
BONUS HA! Geekbench is a client computer benchmark and not a server benchmark and that Raptor/Low-End SKU is really not going to be what most server clients will be using for production workloads. But you keep on spinning your yarns, BrollyChipman, as it’s actually interesting to see your repeated failed attempts at proper server comparsions.
How you can continue your failed attempts over and over without success points more in the direction of that famous definition of insanity.
You still are not understanding Price/Performance with TCO and how that factors in to server market sales in the face of stiff competition. Really comparing one server maker’s Power9 solution and not some of the other Power systems makers. You just can not get x86 out of your brain, namely Intel’s version of x86 that still needs more work to fix all of the security issues with new security issues just found in the last few months.
AMD’s pricing and performance for that lower Epyc/SP3 MB Platform price is Intel’s most pressing problem from an x86 market standpoint. But x86 is not the only game in town and Intel’s getting that competition for the lower end server market from ThunderX2 and other ARM/ARM ecosystem server makers. Power9 is there and power10 on Samsung’s 7nm process will be incoming in 2020. AMD’s Epyc/SP3 MB platform’s, 8 memory channels per socket and with 128 PCIe lanes, feature set still leads Intel’s current and future offerings that are not custom. So it’s mostly Intel’s only 6 memory channels per socket and lower numbers of PCIe lanes that cost extra because of Intel’s market segementing by PCIe lanes and other CPU/MB platform features.
Intel still can not pivot fast enough and that 10nm fiasco is more the banana peel at Intel’s pivot point that’s got Intel sliding sideways instead of pivoting forward. Intel’s going sideways towards that open manhole over the lower gross margins septic flow. And Intel can not continue to milk that CPU supply shortage for too much longer as market share will find a new supplier PDQ, what with Epyc/Naples in unconstrained production and Epyc/Rome getting ready to begin it’s ramp up to volume production also.
With 72 threads and that
With 72 threads and that means 18 core part with SMT4, since 9 core part does not exist. Not low end part at all. Also notice currently its the only Power9 entry available which shows how extremely rare this processor is in the wild or in any measureable use by people outside of supercomputer or mainframe facilities. Poor single thread performance and even worse multi-threaded performance with basic simple benchmarks like Geekbench. You can find many other processors there ranging from obscure ones like VIA Kaixian up to high end ones like Xeons from servers. Many engineering sample leaks also happens there at Geekbench where new processors are being tested.
AMD’s problem is always (behind) schedule and (low) supply. Look at how long they took to get Epyc into the real world servers from their soft launch. Also look at their Embedded and Enterprise division profits in their earnings report. Despite Intel processor shortage for past quarters, AMD does not seem to be able take much advantage at all. That is why they still have single digit market share.
Meanwhile ARM is still lingering around with the lowest market share. Guess you forgot about Intel’s Atom Cxxxx series and Xeon D series low power processors. Example, Facebook is using Xeon Ds. The world’s most efficient supercomputers use Xeon Ds as shown in the Green500 list https://www.top500.org/green500/lists/2018/11/ You don’t see those ARM marketing comparing against these. They always compare against bigger Xeons with higher power consumption.
You Know Damn Well that
You Know Damn Well that Server SKUs take longer to be vetted/certified by the companies that use Server offerings. So Zen-1 had to go through the nominal amount of vetting and then some because Zen was a brand new x86 micro-arch.
AMD’s Zen/Zeppelin Die production had greater than 80% Die/Wafer yields owing to the Zen/Zeppelin Modular/Scalable DIE design so really you continue to make yourself more the fool with each failed retort.
AMD had Zen/Zeppelin certified on GlobalFoundries 14nm(Licensed from Samsung Process) so if any excess wafer start capacity was needed then Samsung’s Fabs could also be used. And do not tell me that you are not aware of the Modified Wafer Supply agreement that was signed several years in advance of Zen-1 being RTM! So AMD had no issues with supply with regards to any demand that GF could not meet with regardes to any its Zen Epyc/Naples based 14nm parts.
Brolly(chipman) you are purely spreading FUD and have no interest in the truth, so really you can only continue to look even more the most egregious fool!
And Just Look to Intel’s current 14nm Wafer Supply issues as a result of that failed 10nm node and the PC/Laptop OEMs who can not get sufficient supplies of consumer Intel parts. Even some OEM’s in their earnings calls are blaming Intel for lost revenues but still you can not see the irony of your FUD against AMD regarding the very same issue!
You are very well into earning that title of the very most egregious fool, Brolly(chipman)!
Its already 2019, but Epyc
Its already 2019, but Epyc launched in 2017 and almost 2 years coming soon but still only garnered single digit percentage. All of AMD’s launches had been soft type, sometimes refered to as “paper launch”. Another example look how long it took for AMD’s low power Epyc Embedded to trickle out into the real world from the time first launched. Look at STH’s (ServeTheHome)articles about this, for example https://www.servethehome.com/piecing-together-the-iei-puzzle-amd-epyc-3000-spotted-in-the-wild/
“We ripped off the case and heatsink with great speed to verify it was indeed the first AMD EPYC 3000 series platform that we have seen outside of AMD demos. The AMD EPYC 3000 series has been hard to find while the V1000 launched at the same time we saw in quite a few places.”
STH was not able to review it until 2019 this year https://www.servethehome.com/amd-epyc-3201-8-core-benchmarks-review-and-milestone/ Just like what happened to Epyc, half a year gone before it trickles out.
Here’s some new Metrics for
Here’s some new Metrics for ya, Brollyanna!
“The Epyc 7371 started sampling last November, and it is specifically aimed at workloads where single-threaded performance is as important as the number of threads per box, and wattage is less of a concern because of the need for faster response on those threads. Think electronic design automation (one of the keys to driving Moore’s Law, ironically), data analytics, search engines, and video transcoding. In any event, AMD Epyc 7371 and Intel Xeon SP-6154 Gold chips have essentially the same SPEC floating point performance, and the AMD chip, at $1,550, costs 56 percent less than the Xeon in this comparison, which has a list price of $3,543.” (1)
Now that’s price/performance at its most basic with the Same SPEC floating point performance metrics and the Epyc part costing 56% ->LESS<-! Judge Farnsworth: What Say You, Single Female Lawyer, concerning those metrics! (1) "Back To The HPC Future With Next Generation AMD Epyc Processors April 4, 2019 Timothy Prickett Morgan " https://www.nextplatform.com/2019/04/04/back-to-the-hpc-future-with-next-generation-amd-epyc-processors/
So, why market uptake of Epyc
So, why market uptake of Epyc not as huge as Xeons? As mentioned in the other reply, its always (behind) schedule and (low) supply. Intel’s short supply is because datacenter vendors and manufacturers were buying left and right every Xeon available. That is why even Intel told them to look at Epyc due to short supply. Those Xeon Gold 8154 are not the new Cascade Lake but the older Skylake SP.
Meanwhile new Cacade Lakes are not really the same as it had many improvements as shown in the benchmarks which occassionally even a single Cascade Lake can outperform a dual Epyc machine as this example https://openbenchmarking.org/embed.php?i=1904023-HV-POWER9CAS39&sha=2f8c46b&p=2 That is unlike the previous generation.
And for faster response such as context switching https://openbenchmarking.org/embed.php?i=1904023-HV-POWER9CAS39&sha=d473b09&p=2 yet again Cascade Lakes are better.
No Intel is in short supply
No Intel is in short supply because Intel took too much wafer start production offline for that Failed 10nm retooling/10nm certification process. But Intel is actually taking advantage of that wafer start suppy issue to keep its margins inflated in the face of AMD’s Epyc/Naples Price/Performance competition.
Intel cares more about the Wall Street Quant’s Gross Margin Basis points metrics and its share values than losing server market share to AMD currenty. Intel’s manegement is in a state of metaphysical angst regarding Intel’s share value that’s going to fall alongside any falling Gross Margin Basis Points that those Wall Street Quants are so good at sussing out from any company’s data.
Just look at Intel’s forward thinking market statments in the past few earnings reports calls and Gross Margins are going to have to come down to prevent AMD from taking too much server market share too quickly.
Look at AMD’s doubling of server SKU orders between Q3 and Q4 of 2018 and that can grow market share very quickly if any doubling continues into 2019 and beyond.
Come on Dunderhead, just take a chess board and put one grain of rice on the first square(Start at any corner and go from there) and double that on the next square to 2 grains and then 4 on the next etc. And yes the Wall Street Quants can look at AMD’s Q3 to Q4 doubling of unit sales and create that supply/demand curve based on that and the previous sales quarters for Epyc/Naples that are again based on some price/performance metrics to arrive at a nice function that’s accurate to within 3-5 sigma to estimate AMD’s Market Share/Revenue growth potential.
Cacade Lakes made it into
Cacade Lakes made it into Cray right at launch https://www.servethehome.com/cray-intel-xeon-platinum-9200-8200-gold-6200-support/
Tell me how long (in months) does Epyc take from launch before making it into Cray? Once again you fail to see the hidden problem.
The unofficial code name for
The unofficial code name for Intel’s Platinum 9282 400 Watt 56 core processor SKU is “George Foreman” and the Platform’s code name is “Grill”.
Let’s look at some
Let’s look at some GigaFlops/Watt figures on that 9282 and compare that to AMD’s MI50/MI60 or Any Of Nvidia’s Volta based Tesla accelerator SKUs.
Because that’s why Intel Hired Raja and not because of some discrete/integrated Gaming graphics potential. Raja was hired to keep Intel from losing even more Server/HPC business to Epyc/Radeon Pro WX/Instinct or Nvidia Volta/Tesla SKUs paired with Power9s/10s! And that’s with both AMD and Nvidia with their GPUs able to trounce Intel’s CPUs in the GigaFlops/Watt metrics!
Oh those Intel Gross Margins over a few years time will have head fruther south than thay have had to go since Opteron was at its around 23% server market share number!
Oh the Gross Margin Pain, Will Robinson, the Terrible Terrible Pain! Oh My Intel Gross Margin Basis Points in the hands of those miserable Wall Street Quants! Oh the Pain the PAIN[Almost Faints] while moaning out those affectations in a state of metaphysical angst!
Seems like Intel is being
Seems like Intel is being lazy and isn’t being forthcoming with any plans to bring the 100GbE to the consumer market.
1GbE is beyond ancient, and 10GbE is getting really long in the tooth. 40GbE is already trailing out, thus we need to just stop neglecting the consumer market and just bring the consumer market to modern networking standards.
The consumer market is not
The consumer market is not ready for even 10GbE for the mast part without PCIe 4.0, or PCIe 5.0, in the ubiquitous state on PCs and especially on laptops.
TB3 is 40Gbs so that’s too many PCIe 3.0 lanes on most OEM laptops where Dell/Others, one some Laptops, took to only providing 2 PCIe 3.0 lanes to the TB3 controller on laptops and that’s not enough PCIe connectivity to even get close to driving a TB3 controller at full bandwidth.
PC users can get their own 10GbE but laptop users are not able to easily do the same with the current state of the PCIe standards that’s PCIe 3.0 based.
Intel’s TB3 adopion rate was more hendered on laptops by the PCIe 3.0 standard and Laptop OEMs cheaping out on their laptop’s MB designs.
The consumer market is unwilling to pay for 10GbE and still is to some degree even though the costs have come down.
100 GbE is costly and really would need PCIe 4.0 to be readily available on consumer devices. The server market SKUs can make use of the fastest GbE because those come with sufficient PCIe/Other lanes that supply the necessary connectivity to the platform. The server market also has IP for delivering PCIe siginaling over Ethernet(ExpEther).
Laptop OEMs have yet to begin widespread adoption of USB 3.1 Gen 2/10Gbs(Rebranded to USB 3.2 Gen 2) for similar reasons to TB/TB3 not being fully made use of. And USB 3.2 Gen 2×2(20Gbs) is adopted and TB3 is now also part of the USB 4.0 standard along with all the other USB IP/Legacy IP.
Not only keep selling but
Not only keep selling but also introducing more processors with the “Spoiler” security hole but No effective solutions, amazing!
Even more amazing, Intel and OEMs keep flooding the market with the “Spoiler Inside” products without warning labels to keep customer informed!