PC Perspective Podcast #539 – Intel’s Big Enterprise Updates, Corsair’s Ultra-Efficient PSU, and More!

6 Comments

1. 

   Dvon of Edzore on April 5, 2019 at 7:01 pm

   Glad you went with the cat
   Glad you went with the cat instead of the calf photo.

   Reply
2. 

   5nmAndAlmostDoubleTheCircuitDensityForTSMC on April 6, 2019 at 8:20 pm

   5nm squeez from TSMC, Risk
   5nm squeez from TSMC, Risk Production starts.

   According to Wikichip(Fuse) TSMC’s 7 nm node yields an estimated logic density of 96.27 MTr/mm² compared to:

   “it was disclosed that they are targeting a 1.8x compaction ratio compared to their 7 nm DUV node. Based on that, we estimate a gate pitch of 48 nm and a metal pitch of 30 nm for an estimated density of 171.3 MTr/mm².” (1)

   (1)

   “TSMC Starts 5-Nanometer Risk Production”

   https://fuse.wikichip.org/news/2207/tsmc-starts-5-nanometer-risk-production/

   Reply
3. 

   Paul A. Mitchell on April 7, 2019 at 8:56 pm

   Josh et al.: Many thanks for
   Josh et al.: Many thanks for your timely overview of the speed trends the storage industry has seen in recent years.
   We’ll be looking forward to your coverage of the PCIe 4.0 roll-out. I wrote a private email message to Josh, with some topics I would love to hear all of you tackle in the coming months e.g NVMe M.2 + 2.5″ both @ 16G. Keep up the good work!

   Reply
4. 

   Paul A. Mitchell on April 8, 2019 at 6:03 pm

   p.s. A few footnotes to add
   p.s. A few footnotes to add to the above:

   fn 1: some sites are warning that cable length
   could be limited by PCIe 4.0’s 16 GHz clock

   fn 2: is Intel planning to increase the number
   of PCIe lanes in their DMI channel?
   or leave it as is, and harness the 2x bandwidth?

   fn 3: can you inquire at ASUS and ASRock to ask
   if they plan to upgrade edge connectors on their
   “4×4” add-in cards? e.g. ASRock Ultra Quad M.2 card

   fn 4: the 2x bandwidth should make it possible
   to do what “der8auer” did with 2 x ASUS 4×4 AICs
   but with only 1 x ASUS 4×4 AIC @ PCIe 4.0, yes?

   fn 5: is Intel planning to make any major changes
   to their VROC dongle? where does one purchase same?

   fn 6: a serious review of AMD’s latest RAID software
   for their Threadripper systems would be appreciated

   fn 7: for a while, we were considering a new build
   using the ASRock X399M motherboard (mATX form factor)
   and a fresh install of Windows 10 onto the ASRock
   Ultra Quad M.2 card; ASRock tech support were
   quick to reply with detailed instructions to do same

   fn 8: why don’t motherboard vendors face the music
   and upgrade their chipsets with support for all
   modern RAID modes on integrated U.2 / M.2 ports?
   all modern RAID modes have been available with
   integrated SATA ports for many years now

   Reply
   • 

     MBForwardCompatablilityNotGuaranteedOnSomeFeatureSets on April 8, 2019 at 8:17 pm

     “fn 1: some sites are warning
     “fn 1: some sites are warning that cable length
     could be limited by PCIe 4.0’s 16 GHz clock”

     That’s MB Trace length/other Trace/Signaling metrics on any MB that’s not designed vetted/certified for PCIe 4.0 signaling and is not really guaranteed to support the new standard.

     So maybe only the first/closest PCIe slot can possibly work with any farther slots unable to support PCIe 4.0 without signal repeaters being engineered into the MB.

     It’s best to get the MB that’s been vetted/certified for PCIe 4.0 support because any AM4 MB socket compatibility is backward compatible but not always forward compatible. So most PCIe signaling may have to remain PCIe 3.0 because of lack of the proper PCIe 4.0 engineering design/hardware on older AM4 MBs.

     Being AM4 socket compatible does not guarantee forward comparability for some MB/Other feature sets.

     P.S. Laptops need PCIe 4.0 more than PCs as laptop SKUs are always PCIe lane constratied.

     Reply
     • 

       Paul A. Mitchell on April 10, 2019 at 2:43 am

       Many thanks for the
       Many thanks for the clarification.

       So, if I read you squarely, a “simple” BIOS update to upgrade a MB to PCIe 4.0 could be somewhat deceptive, particularly if lower PCIe x16 slots just stop working because they can’t handle 16G signals.

       Is that a fair summary?

       I hope AMD addresses this potential pitfall before their Tech Support staff get flooded with questions which those staff can’t solve.

       If I understand your points enough, then an updated BIOS should make intelligent decisions that set an 8G clock on the lower PCIe slots if they can’t oscillate at 16G.

       I’m all for progress, particularly with upstream bandwidth; however, I don’t agree that prosumers should be treated as guinea pigs with a very nasty hardware bug — which only appears because the MB vendor encouraged BIOS updates that are not fully tested.

       Reply

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