GIGABYTE Teases Upcoming PCIe 4.0 NVMe SSD – Coming Soon

Source: ComputerBase GIGABYTE Teases Upcoming PCIe 4.0 NVMe SSD – Coming Soon

GIGABYTE Takes to Twitter to Tease Gen4 SSD Ahead of Computex

GIGABYTE’s Japanese AORUS Twitter account posted a teaser of a mysterious PCIe 4.0 NVMe SSD which is “coming soon”, and with Computex nearly upon us we should know more about it soon. ComputerBase (German language) has the story and references the previously revealed Phison Gen4 SSD controller shown at CES, though the exact controller within this unannounced drive has, naturally, not been confirmed (with only a cagey “it’s a secret” in reply to a question about it).

Assuming it could be using a Phison E16 controller we would be looking at PCIe 4.0 x4 SSD with 8 channels supporting 96-layer TLC 3D NAND. The ComputerBase article also points out that Silicon Motion will also have a PCIe Gen4 option with their planned SM2264 controller, which has been on the company’s roadmap since 2017. We await further details, and with both GIGABYTE and Phison attending Computex we will hopefully have a more official announcement in the coming days.

GIGABYTE Teases Upcoming PCIe 4.0 NVMe SSD - Coming Soon - Storage 2
"Phison predicted sequential transfer rates of up to 4,800 MB / s in January and 4,400 MB / s in writing, as well as up to 900,000 IOPS in the random reading / writing of 4K data. Ultimately, performance depends not only on the controller, but also on NAND flash, cache configuration, and firmware. The rumor mill even speaks of 5,000 MB / s reading and 4,400 MB / s writing for the Aorus NVMe Gen4 SSD and expects the use of 96-layer TLC 3D NAND from Toshiba and Western Digital."

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Sebastian Peak

Editor-in-Chief at PC Perspective. Writer of computer stuff, vintage PC nerd, and full-time dad. Still in search of the perfect smartphone. In his nonexistent spare time Sebastian's hobbies include hi-fi audio, guitars, and road bikes. Currently investigating time travel.


  1. Casper042

    With PCIe 3.0 NVMe drives already hitting 3400 MB/s fairly consistently across multiple vendors’ top tier models, 4000/4400/4800 all mentioned in the article seem a bit Meh to me.

    4.0 should double the per lane bandwidth, so 4 GB/s to 8GB/s.
    If we assume 3400 is approximately as good as we can get due to protocol overhead and such, I’ll be more impressed when we see a 6000MB/s or higher model SSD.

    I’ve also heard in some cases, especially Enterprise, we may see the adoption of 4.0 drop the lane count down from x4 to x2 so you can simply fit more drives, instead of faster drives. Wonder if this is a side effect of the upcoming invasion of Intel DC-PMM which will eat everyone’s lunch from a Latency and IOPs perspective.

    • Sebastian Peak

      I agree that 30 – 40% increases aren’t all that compelling, but that’s an 8-channel controller with less performant NAND. Silicon Motion has a 16-channel controller (SM2270) for PCIe Gen3 x8, and something along those lines adapted to Gen4 x4 would be very interesting. You’re spot on with the enterprise application scenario…x2 interface for more drives on available lanes.


      Generally agreed but note 3400 MB/s is being hit by 500GB+ NVMe SSDs. Take a look at 250GB drives such as the Samsung 970 Evo Plus and you’re looking at only 2300 MB/s write speed (250GB WD black only achieves 1600 MB/s writes). If the benchmarks above are right you’re getting near double the performance at the lower capacity.

      This does support your hypothesis at higher capacities we’re seeing bottlenecks such as protocol overhead. But note there is something more fundamental going on – I/O speeds are so high now that the bottleneck is becoming the RAM and CPU because of the way modern OSes and their kernels are designed (see the recent hackernews discussion on the paper “I/O is faster than CPU – Let’s Partition Resources and Eliminate OS Abstractions”).

      Notably write speeds are actually higher than read on the above chart. I remember Allyn Malventano saying this should actually be the case (you can dump new writes on any piece of NAND that the OS says you can write to and that should be quicker than reads where you have to do the branching work to find the particular data).

  2. Hakuren

    Wholeheartedly agree. Dropping lines to x2 will yield more benefits than blistering fast sequential writes achievable only at ridiculously high QD and very specific conditions. I would love to double my NVMe count from 7 to 14 on TR4 socket without sacrificing any of the rendering cards.

    PCIe Gen4 is nothing to shout about. Not for a long haul as 2021 is already on course for Gen 5 by Intel.


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