TSMC published a blog post last Wednesday that is called, “Moore’s Law is not Dead”. First, they reiterate that Moore’s Law is about density, not performance. It used to be that a denser semiconductor manufacturing would reduce cost, increase performance, and reduce power consumption. Performance has plateaued for a while, but density is still progressing.
The article goes on to talk about “system level density”.
While this has the marketing spin feel, it is backed with an experimental, almost 2500mm2 surface area interposer that can mount two 600mm2 dies and eight 75mm2 HBM memory packages. The article goes on to note that a common bottleneck in computing is keeping the logic fed with data. This is mostly true for parallel processors, such as GPUs, but TSMC also mentions dedicated AI processors. With the RAM and the processors all on the same interposer, bandwidth goes up and latency goes down much easier than separate components on a large circuit board.
Of course, some day we’ll transition to a new compute medium. We don’t need to push electrical waves down a semiconductor at radio frequencies. We will figure out a new paradigm, whether that’s quantum, light down an optical integrated circuit, or something else entirely. It will be interesting to see whether that transition is pioneered by the existing players.
i think eventually we will get away from litho processes and start 3d printing circuits. gallium nitride might come first (or whatever its called) but eventually i think the same thing will happen to photo lithography as what happened photographs. replaced with a machine that assembles circuits out of atoms just like photographs are assembled out of tiny microscopic dots of ink now. they will probably just look like they are growing out of a machine slowly like fingernails in great big sheets like plywood. growing one atomic layer at a time
Yeah, 3D is another way around it. I’m hoping we’ll see something that boosts clock frequencies significantly, though.
Who’s huge device is that? Way to bury the lede. 😉
It’s an experimental interposer. As far as I know, it’s something that TSMC made to pitch to other companies.
AFAIK, HBM2 is closer to 100 square mm per die; I have seen 92 for Hynix’s implementation I think. Does someone else have it smaller? I am also curious as to how big of gpus we will actually get on 7 nm. It may be very difficult to get sufficient yields for a 600 square mm die to be reasonable.
I have been thinking that AMD will go with an interposer for their IO die eventually. I don’t know if they will actually place the cpus on the interposer though. It may make more sense to keep them as they are. An active interposer would allow all of the larger transistors required to drive external interfaces to go into the interposer. They could then stack 7 nm chips on top for the logic parts of the die. That would allow for massive cache to be placed on the interposer with the memory controllers without a large, expensive interposer.
For gpus, it is unclear which way they are going. For many gpu compute applications, two smaller gpus with half the compute and half the bandwidth perform just about the same as a single large gpu. For HPC, I expect they will do gpus with HBM on the interposer and then connect multiple interposers together (possibly on the same board) with infinity fabric. I don’t what they will do for gaming though, where multiple, separate gpus has not been well supported. If you are already using an interposer for HBM, then I could imagine a gpu split into multiple chiplets but still acting as a monolithic gpu. They could also be two essentially separate gpus with just really high bandwidth between them. I am leaning towards just multiple, single gpu interposers connected together through the pcb for anything cooking out soon.