Samsung Introduces Faster, Higher Capacity High Bandwidth Memory for HPC Applications
Samsung announced its 3rd generation of HBM 2E memory today aimed at accelerating AI analytics, advanced graphics, and other high performance computing (HPC) and supercomputer workloads. The new 16GB memory packages utilize eight stacked 16Gb DRAM dies and offer up 410 GB/s of bandwidth per stack and 3.2 Gbps transfer speeds.
The eight 10nm-class (1y) 16Gb dies along with a buffer chip are stacked together into a HBM2E package using 40,000 TSVs (through silicon vias) with each die having over 5,600 microbumps. Samsung is using its latest DRAM and proprietary circuit designs to offer twice the capacity of second-generation 8GB “Aquabolt” HBM2 along with increased performance and power efficiency. Samsung is rating the current HBM2E at 3.2 Gbps and 410GB/s of bandwidth, but the technology has been tested at up to 4.2 Gbps transfer speeds and 538 GB/s of bandwidth per stack for certain future applications. At the highest tested speeds, Samsung puts the “Flashbolt” HBM2E at 1.75x the performance of Aquabolt’s 307 GB/s bandwidth.
Volume production of 3rd generation HBM2E will begin within the first half of this year while continuing to produce 2nd generation HBM2 products. Advances in High Bandwidth Memory will have the most impact in the enterprise space with specialized workloads that can benefit from the increased bandwidth.
"With the introduction of the highest performing DRAM available today, we are taking a critical step to enhance our role as the leading innovator in the fast-growing premium memory market," said Cheol Choi, executive vice president of Memory Sales & Marketing at Samsung Electronics. "Samsung will continue to deliver on its commitment to bring truly differentiated solutions as we reinforce our edge in the global memory marketplace."