Intel Architecture Day 2020: Tiger Lake, Xe, and SuperFin

Intel held its Architecture Day 2020 this week, with this virtual press event providing some new disclosures as well an update on the progress Intel is making on their “six pillars of technology innovation strategy”.

We will look at some of the consumer-focused news in this post, beginning with an update on Intel’s 10nm process.

10nm SuperFin Technology

Intel shared details on the advancements made to their 10nm process, which they are calling “the largest single, intranode enhancement in the company’s history”, adding that it delivers a “performance improvement comparable to a full-node transition”.

And, rather than resorting to the maligned “+” nomenclature, we have a new marketing term for the advancements to Intel’s 10nm process: SuperFin.

After years of refining the FinFET transistor, Intel is redefining the technology to enable the largest single intranode enhancement in its history, delivering performance improvement comparable to a full-node transition.

10nm SuperFin technology combines Intel’s enhanced FinFET transistors with Super metal insulator metal capacitor. SuperFin technology offers enhanced epitaxial source/drain, improved gate process and additional gate pitch to enable greater performance by:

• Enhancing epitaxial growth of crystal structures on the source and drain, thus increasing strain and reducing resistance to allow more current through the channel.
• Improving gate process to drive higher channel mobility, which enables charge carriers to move more quickly.
• Providing an additional gate pitch option for higher drive current in certain chip functions that require the utmost performance.
• Using a novel thin barrier to reduce resistance by 30% and enhance interconnect performance.
• Delivering a 5x increase in capacitance within the same footprint when compared to industry standard, driving a voltage droop reduction that translates to dramatically improved product performance. The technology is enabled by a new class of “Hi-K” dielectric materials stacked in ultra-thin layers just several angstroms thick to form a repeating “super lattice” structure. This is an industry-first technology that is ahead of current capabilities of other manufacturers.

The first processor family based on SuperFin? Tiger Lake.

The Tiger Lake SoC

Combining Intel’s Willow Cove CPU and Xe graphics architectures, Tiger Lake is an entirely new mobile SoC. The successor to the Sunny Cove core found in Ice Lake, Intel says the process advancements from their 10nm SuperFin technology “delivers more than a generational increase in CPU performance with large frequency improvements and increased power efficiency”.

Tiger Lake SoC architecture offers:

• New Willow Cove CPU core with significant frequency uplift leveraging 10nm SuperFin technology advancements.
• New Xe graphics with up to 96 execution units (EUs) with significant performance-per-watt efficiency improvements.
• Power management – autonomous dynamic voltage frequency scaling in coherent fabric, increased fully integrated voltage regulator efficiency.
• Fabrics and memory – 2x increase in coherent fabric bandwidth, ~86GB/s memory bandwidth, validated LP4x-4267, DDR4-3200; LP5-5400 architecture capability. 
• Gaussian Network Accelerator (GNA) 2.0 dedicated IP for low-power neural inferencing offloading from the CPU. ~20% lower CPU utilization on GNA vs. CPU (running noise suppression workload).
• IO – Integrated TB4/USB4, integrated PCIe Gen 4 on CPU for low-latency, high-bandwidth device access to memory.
• Display – up to 64GB/s of isochronous bandwidth to memory for multiple high-resolution displays. Dedicated fabric path to memory to maintain quality of service. 
• IPU6 – up to six sensors with 4K30 video, 27MP image, up to 4K90 and 42MP image architectural capability.

As to availability of these new mobile processors, Intel states that “Tiger Lake is in production, and shipping to customers”, with OEM systems “expected for the holiday season”.

Xe Graphics Updates

Intel provided a deep dive into their upcoming low-power Xe graphics to be found in Tiger Lake products, appropriately called Xe-LP. This is part of the company’s overall GPU strategy announced in 2019, beginning with Xe-LP and eventually encompassing enthusiast desktop as well as datacenter and HPC.

Xe-LP: Integrated and Entry-Level

On the consumer side, Intel focused most of their architectural discussion on the aforementioned Xe-LP graphics to be found in Tiger Lake.

Xe-LP is Intel’s most efficient architecture for PC and mobile computing platforms with up to 96 EUs, and comes with new architecture designs including asynchronous compute, view instancing, sampler feedback, updated media engine with AV1 and updated display engine. This will enable new end-user features with instant game tuning, capture, and stream-and-image sharpening. On software optimization, Xe-LP will have driver improvements with a new DX11 path and optimized compiler.

Xe-LP is a 1.5x larger engine, offering up to 96 execution units compared to 64 EUs with Gen11. Based on the new 10nm SuperFin technology, Xe-LP provides what Intel is calling “significant performance-per-watt efficiency improvements”, and offers up to 48 texels and 24 pixels per clock, with 1536 flops per clock.

Xe-HGP: Enthusiast Level Graphics

The Xe GPU strategy now includes a new variant called Xe-HPG, which will be the enthusiast-level product when it launches next year – marking Intel’s return to the enthusiast GPU space for the first time in more than 20 years (the Intel 740 launched the AGP interface in 1998).

Intel introduced a new Xe microarchitecture variant, Xe-HPG, a gaming-optimized microarchitecture, combining good performance-per-watt building blocks from Xe-LP, leveraging the scale from Xe-HP for a bigger configuration and compute frequency optimization from Xe-HPC. A new memory subsystem based on GDDR6 is added to improve performance per dollar and Xe-HPG will have accelerated ray tracing support. Xe-HPG is expected to start shipping in 2021.

Of particular interest in the quote above, it was revealed that Xe-HPG will offer hardware ray-tracing support.

As to Intel’s first Xe-LP based discrete GPU product (code-named “DG1”), it is currently in production and “on track to start shipping in 2020”. For early developer access Intel’s DG1 is already available within the Intel DevCloud.