TSMC’s 3nm Is On Track

A Full Node Stride

TSMC have stated that their 3nm lines should be online later this year and describe it as a much larger change than their switch to 5nm.  The process will offer up to 70% density increase for logic components, a boost in performance up to 15% and power reduction in the neighbourhood of 30%.  This was not cheap to accomplish, somewhere between $25-28 billion USD were spent on this, an increase in capital expenditure of $10 billion compared to last year.

As opposed to using a gate all around (GAAFET) design which TSMC did in fact design and Samsung will be using for their 3nm lines, TSMC have decided to go with a refined FinFET design, far more familiar to silicon junkies.  Samsung is scheduled to start slinging their 3nm silicon around the same time, with Intel still looking at 2025 as a launch date.

Part of the capital expenditure is scheduled to go to the plant they intend to build in Arizona which will not be finished in time for some people’s predicted dates, TSMC is stating that 2024 is their intended target and that the fab will have a capacity of 20K wafers per month.  This will help them in the changing environment that we are facing.  It could shorten supply chains and may avoid the international tariffs which the US is levying against many overseas companies.  It should also help alleviate the loss of Hauwei as a customer, for reasons at least partly related to those tariffs.

The Register offers a few links to delve deeper into this announcement here.