It’s Not An APU, It’s What Happens When Ponte Vecchio Meets Sapphire Rapids
Intel has some serious HPC plans for the future, combining x86 CPU cores and Xe GPU cores into a single package of your choice called an XPU. Rialto Bridge products will ship in a large array of packages, some with x86 CPU cores and Xe cores, while others might be strictly x86 cores or Xe cores, which you can choose to best meet your processing needs. The performance improvements they are suggesting this will bring are impressive; suggesting you should expect five times the performance per watt, memory capacity, and memory bandwidth compared to the competition. That is something NVIDIA is unlikely to take lying down.
Intel also talked up Ponte Vecchio at the International Supercomputing Conference in Hamburg, Germany as we still have not actually seen it in the wild. We will soon have more details as several Intel based supercomputers should be booted up soon, including the Aurora supercomputer at Argonne National Laboratory, among others.
We know Ponte Vecchio will make use of HBM2e memory, which implies the existence of HBM3 being used in Rialto Bridge to account for the increased memory bandwidth. The new XPU will likely also make use of PCIe 5.0 and 6.0 to ensure it’s pipes are thick enough to handle all this increased bandwidth. Pop by The Register, or look below for a link to Serve The Home’s coverage if you are curious about the future of Intel’s high powered silicon, including this new Falcon Shores XPU design.
The semiconductor giant shared the details Tuesday in a roadmap update for its HPC-focused products at the International Supercomputing Conference in Hamburg, Germany.