Today ARM is announcing their partnership with Xilinx to deliver design solutions for their products on TSMC’s upcoming 7nm process node. ARM has previously partnered with Xilinx on other nodes including 28, 20, and 16nm. Their partnership extends into design considerations to improve the time to market of complex parts and to rapidly synthesize new designs for cutting edge process nodes.
Xilinx is licensing out the latest ARM Artisan Physical IP platform for TSMC’s 7nm. Artisan Physical IP is a set of tools to help rapidly roll out complex designs as compared to what previous generations of products faced. ARM has specialized libraries and tools to help implement these designs on a variety of processes and receive good results even on the shortest possible design times.
Design relies on two basic methodologies. There is custom cell and then standard cell designs. Custom cell design allows for a tremendous amount of flexibility in layout and electrical characteristics, but it requires a lot of man-hours to complete even the simplest logic. Custom cell designs typically draw less power and provide higher clockspeeds than standard cell design. Standard cells are like Legos in that the cells can be quickly laid out to create complex logic. Software called EDA (Electronic Design Automation) can quickly place and route these cells. GPUs lean heavily on standard cells and EDA software to get highly complex products out to market quickly.
These two basic methods have netted good results over the years, but during that time we have seen implementations of standard cells become more custom in how they behave. While not achieving full custom performance, we have seen semi-custom type endeavors achieve appreciable gains without requiring the man hours to achieve fully custom.
In this particular case ARM is achieving a solid performance in power and speed through automated design that improves upon standard cells, but without the downsides of a fully custom part. This provides positive power and speed benefits without the extra power draw of a traditional standard cell. ARM further improves upon this with the ARM Artisan Power Grid Architect (PGA) which simplifies the development of a complex power grid that services a large and complex chip.
We have seen these types of advancements in the GPU world that NVIDIA and AMD enjoy talking about. A better power grid allows the ASIC to perform at lower power envelopes due to less impedence. The GPU guys have also utilized High Density Libraries to pack in the transistors as tight as possible to utilize less space and increase spatial efficiency. A smaller chip, which requires less power is always a positive development over a larger chip of the same capabilities that requires more power. ARM looks to be doing their own version of these technologies and are applying them to TSMC’s upcoming 7nm FinFET process.
TSMC is not releasing this process to mass production until at least 2018. In 1H 2017 we will see some initial test and early production runs for a handful of partners. Full blown production of 7nm will be in 2018. Early runs and production are increasingly being used for companies working with low power devices. We can look back at 20/16/14 nm processes and see that they were initially used by designs that do not require a lot of power and will run at moderate clockspeeds. We have seen a shift in who uses these new processes with the introduction of sub-28nm process nodes. The complexity of the design, process steps, materials, and libraries have pushed the higher performance and power hungry parts to a secondary position as the foundries attempt to get these next generation nodes up to speed. It isn’t until after some many months of these low power parts are pushed through that we see adjustments and improvements in these next generation nodes to handle the higher power and clockspeed needs of products like desktop CPUs and GPUs.
ARM is certainly being much more aggressive in addressing next generation nodes and pushing their cutting edge products on them to allow for far more powerful mobile products that also exhibit improved battery life. This step with 7nm and Xilinx will provide a lot of data to ARM and its partners downstream when the time comes to implement new designs. Artisan will continue to evolve to allow partners to quickly and efficiently introduce new products on new nodes to the market at an accelerated rate as compared to years past.
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Pushing the limits of tomorrow’s technology today: Artisan physical IP for 7nm
ARM Physical IP for TSMC 7nm process technology now available
Gone are the days when FPGAs were used primarily for prototyping. Today, developers can drive quickly and cost-effectively into IoT, embedded vision, cloud computing and other sectors using FPGAs. Xilinx is among the companies that have helped enable this drive in recent years, offering new architectures and products on leading-edge process nodes, including 28nm, 20nm and 16nm.
Each of these nodes can bring with it cost challenges and potential risks that can derail the best engineering intentions. ARM has partnered with Xilinx for four process technology generations to deliver physical IP solutions to speed innovation and minimize cost and risk. The strong partnership continues at 7nm: Xilinx, I am pleased to announce, has licensed the ARM Artisan physical IP platform for TSMC 7nm FinFET (7FF) process technology to develop its next generation of all programmable products.
Cutting complexity to size
ARM Artisan IP for TSMC 7FF technology builds on our success with previous generation FinFET technologies. Foundational physical IP provides the building blocks for a SoC design, creating an interface between the underlying semiconductor process technology and the SoC design itself. A key motivator when developing the platform was to be able to provide all of the benefits of the TSMC 7nm process technology, but abstract away the complexities associated with it for the SoC designer. The ARM Artisan platform not only uses the Front End of Line (FEOL) device to provide compelling performance, but also pays special consideration to the Back End of Line (BEOL). In 7nm technology, this could be the difference between a good SoC and an excellent SoC because unlike previous technology nodes, it’s the BEOL that determines the quality of your performance and results, not just the FEOL device. The unique characteristics of the 7FF process technology meant that we had to invent a new memory development methodology, thus the introduction of memory compilers utilizing a cell based layout. This new memory architecture provides for more consistent patterns in the memory layout, thereby minimizing variation. Minimizing variation leads to less design margin and better memory PPA for use in the SoC.
ARM Cell Based Layout minimizes variation due to consisten patterns in design.
As metallization becomes more challenging logic routability is critical, especially at 7nm FinFET, to determining the performance, power, and area (PPA) of your SoC. Solving routability is not limited to just tackling congestion, you also need to pay special attention to IR (voltage drop) and EM (electromigration). As the process design rules have gotten tighter going from 16/14nm FinFET to 7nm FinFET, the parasitic electrical properties have made it more challenging and complex to design a power grid. A good power grid can help you get significantly better performance and save both power and area in SoC designs. The ARM Artisan Power Grid Architect (PGA) simplifies the development of the power grid; with the knowledge of Artisan logic libraries encapsulated in PGA, the power grid creation is correct-by-construction. As a result, a knowledgeable SoC designer can create a power grid that meets their needs within a matter of hours, versus the several days and iterations it may have taken previously.
Figure 2. Layout utilization of design before using PGA and after using PGA – resulting in 10% area reduction and effective utilization rate improvement of 20%
Our logic library development teams have access to the most advanced ARM Cortex-A CPUs and GPUs, so we are able to test our logic architectures with real-world RTL and solve problems for our customers well before they experience them. This collaboration between physical IP and CPU architecture teams also enables us to develop special logic cells that improve the architectural performance of the CPU.
The signals processed in the SoC may need to interface with other SoCs in a system. To address this, ARM provides a family of General Purpose I/O (GPIO) that supports multiple voltage levels (3.3V and 1.8V) to meet the requirements of various markets segments. ARM GPIOs are programmable and high-performance with innovative low-power features. Smaller than competitive GPIOs, they also meet, or exceed, industry-standard ESD requirements.
ARM and Xilinx have worked closely for years to push boundaries of innovation with each new process node, and the quality of ARM physical IP and this partnership model are extended throughout the ARM partner ecosystem. ARM continues to invest in advanced technology platforms with a view to providing our partners with world-class design solutions, all the while reducing risk by providing high quality foundation IP. Our mission continues to be adding value to SoC designers by solving the advanced semiconductor technology challenge and accelerating adoption. By developing IP in parallel to the process technology development and running multiple test-chips on pre-production PDK to incorporate silicon feedback, ARM helps partners get a head-start on SoC development and reduce technical risk.
ARM Physical IP Platform for TSMC 7nm is available now for evaluation and licensing. If you want to know more about ARM Physical IP platform for TSMC 7nm, please talk to your ARM partner manager.
They should stop using a nm
They should stop using a nm number to names these process nodes. AFAIK,they haven’t actually meant anything in a very long time.
The “nm” is for the gate size
The “nm” is for the gate size and if the gate size is say 10nm then it’s a 10nm process. Now the gate pitch is the distance between gates so that’s another matter. The power savings and switching ability comes from mostly the gate size/gate geometry and the elements used to make that gate and also the gate’s third dimension! And even a “plainer” process has a third dimension or else the gate and the whole shebang would not exist in space/time! Now plainer gates only contact on a very thin plainer boundary layer but these plainer Field Effect Transistors produce an effect into the channel doped into the silicon’s substrate deeper into the 3rd dimension.
The so called 3d finfet process takes the thin plainer boundary layer and wraps it part way around a fin like geometry that allows for more contact area in a smaller 3d space with the thin plainer boundary layer wrapped ¾ of the way around the fin to produce a better circuit contact area with a better field effect produced with better switching characteristics and less leakage. Also the taller the fin the more area relative to the width of the finfet that will make contact at the boundary layer relative to the unwrapped part of the fin so even better switching/less leakage can be had. That Fet in the fin stands for Field Effect Transistor.
The next step is to move from FinFet to gate all around! So It’s mostly gate size/gate geometry that makes the process node(nm) and for the most part the circuit benefits while the gate pitch only figures into to the amount of circuits that can be crammed into a unit area on a die!
Xilinx’s history goes back to
Xilinx’s history goes back to the start of the FPGA market! And I wonder if softbank is looking to invest there also. That ARM Artisan Physical IP platform for TSMC’s 7nm proces is for ARM markets many licensees to get their products to market faster with more efficient use of die space.
From the wikipedia entry on FPGAs Xilinx is also making use of silicon interposers for more fabrication latitude with dies that can be fabricated on the process the best suits their use and combining the dies on an interposer:
“Xilinx’s approach stacks several (three or four) active FPGA die side-by-side on a silicon interposer – a single piece of silicon that carries passive interconnect.[38][39] The multi-die construction also allows different parts of the FPGA to be created with different process technologies, as the process requirements are different between the FPGA fabric itself and the very high speed 28 Gbit/s serial transceivers. An FPGA built in this way is called a heterogeneous FPGA.[40]”
https://en.wikipedia.org/wiki/Field-programmable_gate_array